Hacklet 28 – Programmable Logic Hacks

January 2, 2015 by Adam Fabio 21 Comments

FPGAs, CPLDs, PALs, and GALs, Oh My! This week’s Hacklet focuses on some of the best Programmable Logic projects on Hackaday.io! Programmable logic devices tend to have a steep learning curve. Not only is a new hacker learning complex parts, but there are entire new languages to learn – like VHDL or Verilog. Taking the plunge and jumping in to programmable logic is well worth it though. High-speed projects which would be impossible with microcontrollers are suddenly within reach!

A great example of this is [Tom McLeod’s] Cheap FPGA-based HDMI Experimenting Board. [Tom’s] goal was to create a board which could output 720p video via HDMI at a reasonable frame rate. He’s using a Xilinx Spartan 6 chip to do it, along with a handful of support components. The images will be stored on an SD card. [Tom] is hoping to do some video with the setup as well, but he has yet to see if the chip will be fast enough to handle video decoding while generating the HDMI data stream. [Tom] has been quiet on this project for a few months – so we’re hoping that either he will see this post and send an update, or that someone will pick up his source files and continue the project!

Next up is our own [technolomaniac] with his Arduino-Compatible FPGA Shield. Starting out with FPGAs can be difficult. [Technolomaniac] has made it a bit easier with this shield. Originally started as a project on .io and now available in The Hackaday Store, the shield features a Xilinx Spartan 6 FPGA. [Technolomaniac] made power and interfacing easy by including regulators and level shifters to keep the sensitive FPGA happy. Not sure where to start? Check out [Mike Szczys’] Spartan-6 FPGA Hello World! [Mike] takes us from installing Xilinx’s free tool chain to getting a “hello world” led blinker running!

Still interested in learning about Programmable Logic, but not sure where to go? Check out [Bruce Land’s] Teaching FPGA parallel computing. Actually, check out everything [Bruce] has done on Hackaday.io – the man is a living legend, and a wealth of information on electronics and embedded systems. Being a professor of engineering at New York’s Cornell University doesn’t hurt either! In Teaching FPGA parallel computing, [Bruce] links to Cornell’s ECE 5760 class, which he instructs. The class uses an Altera/Terasic DE2 FPGA board to demonstrate parallel computing using programmable logic devices. Note that [Bruce] teaches this class using Verilog, so all you seasoned VHDL folks still can learn something new!

Finally, we have [Michael A. Morris] with Chameleon. Chameleon is an Arduino compatible FPGA board with a Xilinx Spartan 3A FPGA on-board. [Michael] designed Chameleon for two major purposes: soft-core processors, and intelligent serial communications interface. On the processor side Chameleon really shines. [Michael] has implemented a 6502 core in his design. This means that it would be right at home as the core of a retrocomputing project. [Michael] is still hard at work on Chameleon, he’s recently gotten fig-FORTH 1.0 running! Nice work [Michael]!

Want more programmable logic goodness? Check out our Programmable Logic List!

That about wraps things up for this episode of The Hacklet! As always, see you next week. Same hack time, same hack channel, bringing you the best of Hackaday.io!

Parallax Propeller 1 Goes Open Source

August 7, 2014 by Adam Fabio 60 Comments

OpenPropellerProject OpenSourceProp1Banner

Parallax has embraced open source hardware by releasing the source code to its Propeller 1 processor (P8X32A). Designed by [Chip Gracey] and released in 2006, the 32-bit octal core Propeller has built up a loyal fan base. Many of those fans have created development tools for the Propeller, from libraries to language ports. [Ken, Chip], and the entire Parallax team have decided to pay it forward by releasing the entire source to the Propeller.

The source code is in Verilog and released under GNU General Public License v3.0. Parallax has done much more than drop 8-year-old files out in the wild. All the configuration files necessary to implement the design on an Altera Cyclone IV using either of two different target boards have also been included. The DE0-Nano is the low-cost option. The Altera DE2-115 dev board is more expensive, but it also can run the upcoming Propeller 2 design.

The release also includes sources for the mask ROM used for booting, running cogs, and the SPIN interpreter. [Chip] originally released this code in 2008. The files contain references to PNut, the Propeller’s original code name.

We’re excited to see Parallax taking this step, and can’t wait to see what sort of modifications the community comes up with. Not an Altera fan? No problem – just grab the source code, your favorite FPGA tools, and go for it! Starved for memory? Just add some more. 8 cogs not enough? Bump it up to 16. The only limits are the your imagination and the resources of your target device.

Interested in hacking on a real Propeller? If you’re in Las Vegas, you’re in luck. A Propeller is included on each of the nearly 14,000 badges going to DEFCON 22 attendees. While you’re there, keep an eye out for Mike and The Hackaday Hat!

CPLD Tutorial: Learn Programmable Logic The Easy Way

April 6, 2014 by Adam Fabio 16 Comments

The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. (March 2018: Link dead. Try the Wayback Machine.) Programmable logic devices are one of the most versatile hardware building blocks available to hackers. They also can have a steep learning curve. Cheap Field Programmable Gate Arrays (FPGA) are plentiful, but can have intricate power requirements. Most modern programmable logic designs are created in a Hardware Description Language (HDL) such as VHDL or Verilog. Now you’ve got a new type of device, a new language, an entirely new programming paradigm, and a complex IDE to learn all at once. It’s no wonder FPGAs have sent more than one beginner running for the hills.

The tutorial cuts the learning curve down in several ways. [Carl] is using Complex Programmable Logic Devices (CPLD). At the 40,000 foot level, CPLDs and FPGAs do the same thing – they act as re-configurable logic. FPGAs generally do not store their configuration – it has to be loaded from an external FLASH, EEPROM, or connected processor. CPLDs do store their configuration, so they’re ready as soon as they power up. As a general rule, FPGAs contain more configurable logic than CPLDs. This allows for larger designs to be instantiated with FPGAs. Don’t knock CPLDs though. CPLDs have plenty of room for big designs, like generating VGA signals.

[Carl] also is designing with schematic capture in his tutorial. With the schematic capture method, digital logic schematics are drawn just as they would be in Eagle or KiCad. This is generally considered an “old school” method of design capture. A few lines of VHDL or Verilog code can replace some rather complex schematics. [Carl’s] simple designs don’t need that sort of power though. Going the schematic capture route eliminates the need to learn VHDL or Verilog.

[Carl’s] tutorial starts with installing Altera’s Quartus II software. He then takes the student through the “hardware hello world” – blinking an LED. By the time the tutorial is done, the user will learn how to create a 4 bit adder and a 4 bit subtractor. With all that under your belt, you’re ready to jump into big designs – like building a retrocomputer.

[Image via Wikimedia Commons]

Design Your Own Processor With Verilog

March 1, 2014 by Adam Fabio 17 Comments

Intel-sandy

Designing a computer from scratch is one of the holy grails of hardware design. For programmable logic, designing your own processor is a huge accomplishment. That’s exactly what [zhemao] has done. He created EZ8, an 8 bit processor is written in Verilog. EZ8 has a 3 stage pipeline, which makes design very interesting. Instruction set pipelines have been used in processors for many years. They speed up operation by allowing the processor to execute more than one instruction in parallel. The idea is similar to washing, drying and folding laundry. Most people pipeline their laundry. One load is in the washer, another in the dryer, and a third is being folded. Pipelines aren’t a free lunch though – there are hazards. If one instruction requires the result of an instruction which is still being executed in parallel, there’s a problem. In our laundry analogy this would be like having one sock on the folding table while its mate is still in the dryer. The folding operation must wait for the drying operation to complete before the socks can be paired. This is exactly how assemblers handle the situation – they insert NOPs between known hazard instructions.

[zhemao] didn’t just give us a processor and no support though. He also included an assembler written in OCaml, and an emulator written in C. Several test assembly programs are also up on [zhemao’s] github repo to verify operation. [zhemao] has tested his processor with Altera Cyclone 5 series FPGAs, but it should be possible to port it to other FPGA manufacturers. If you want more information, [zhemao] also has a discussion going on in the ECE subreddit.

[Thanks for the tip LongHornEngineer!]

[Image courtesy of intel]

Designing Flip-Flops With Python and Migen

January 29, 2014 by Brian Benchoff 39 Comments

migen

Flip-flops are extremely simple electronic circuits, forming the basis of clock circuits, memory circuits, buffers, and shift registers. Through his dilly-dallying with digital logic, [Jeffrey] decided he would build his own. Not with Verilog or VHDL, though, but Migen: the Python-based way to build digital circuits with software.

Migen is an interesting tool that makes traditional FPGA programming a lot easier; instead of Verilog or VHDL, Migen allows an FPGA to be programmed in Python. Yes, it’s the tool you’ve been waiting for, and the tutorials make it look pretty easy. After installing Migen, [Jeff] wrote a class for a D flip-flop in only three lines of code. That’s three readable lines of code, and he was able to simulate the flip-flop with gtkwave in another two lines. Compared to learning the complexities of VHDL or Verilog, Migen makes digital logic and FPGA programming a breeze.

[Jeff] has a great tutorial for building a D flip-flop with Migen, but we’d love to see some more complex examples of what can be done with this very cool tool. If you’re building (or have built) something with Migen, be sure to send it in and relate your experiences.

Fubarino Contest: FPGA Pong

December 26, 2013 by Brian Benchoff 2 Comments

pong

For [Eric]’s entry for our Fubarino Contest, he went down to very low-level hardware and created Pong on an FPGA.

[Eric] used a Basys 2 FPGA board to create this virtual, logic gate version of Pong. Output is via the VGA port, multiplayer and an AI player is implemented, and all the required mechanics for Pong – collision detection, button and switch input, and score keeping are also in this project.

The Fubarino contest requires an easter egg, of course, so when the score for the left player reaches 13 and the score for the right player reaches 37 (get it? 1337?), the previously square ball turns into an extremely pixeley version of the Hackaday logo. The Hackaday URL is also displayed, thanks to [Eric]’s FP(V)GA module for displaying text on his FPGA board.

The improved Pong ball and URL only appears when the scores are 13-37, making this an extremely well-hidden easter egg. Video of [Eric] demoing his Pong below.

This is an entry in the Fubarino Contest for a chance at one of the 20 Fubarino SD boards which Microchip has put up as prizes!

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Build An FPGA Microbee In Three (Not So) Easy Steps

October 12, 2013 by Adam Fabio 13 Comments

Microbee,_Melbourne_Museum

[Brad Robinson] was feeling a bit nostalgic for his Microbee, so he rebuilt it in an FPGA. Not once, but three times. For the uninitiated, the Applied Technology Microbee was a Z80 based computer 1980’s. Designed in Australia, the Microbee did not see much popularity outside its home continent. Even so, the introduction to home computers many Australians was on a Microbee. [Brad] actually wrote several programs for the Microbee, including some games sold by Applied Technology themselves.

Fast forward to 2012, [Brad] is learning FPGAs, and wants to build a Microbee in VHDL. The FPGAbee was born. The first iteration of the FPGAbee began with the CPU, which came from the T80 open source VHDL Z80 core. Around this core [Brad] added the video controller, keyboard, and sound. When he started adding disk functionality, [Brad] ran into some problems. He wanted to use a FAT formatted SD card for cassette and hard disk emulation.

The relative complexities of the FAT format meant he would have to use some custom software to make this work. [Brad] decided to run this software on a second Z80 core. Both cores would need access to memory, and this is where [Brad] learned what he calls “a hard lesson in cross domain clocks” on FPGAs. Multiple clock nets can cause major propagation delay issues. [Brad] was able to work through the problems, but it caused him to step back and re-evaluate the entire design. This was the start of FPGABee2.

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