Lightweight Game Console Packs a Punch

Any maker worth their bits will look for new ways to challenge themselves. [Robert Fotino], a computer science student at the University of California, is doing just that: designing and building his own lightweight hobbyist game console that he has appropriately named Consolite.

[Fotino] wrote his own compiler in C++ that converts from C-like languages to a custom-designed assembler that he has dubbed Consolite Assembly. To test his code, he also wrote an emulator before loading it onto the Mimas V2 FPGA board. Presently, Consolite  uses 64KiB of main memory and 48 KiB of video memory; a future version will have 32 bit support to make better use of the Mimas’ 64 MiB of on board ram, but the current 16-bit version is a functional proof of concept.

consolite-status-leds-and-hardware-switches_thumbnailAn SD card functions as persistent storage for up to 256 programs, which can be accessed using the hardware switches on the Mimas, with plans to add user access in the form of saving game progress, storage outside of main memory, etc. — also in a future update that will include audio support.

As it stands, [Fotino] has written his own versions of Breakout, Tetris, and Tron to show off his project.

Not wanting for diligence, [Fotino] has provided thorough documentation of nearly every step along the way in his blog posts and on GitHub if you are looking for guidelines for any similar projects you might have on the back burner — like an even tinier game console.

[via r/FPGA]

Xilinx FPGAs in C for Free

When you think of developing with FPGAs, you usually think of writing Verilog or VHDL. However, there’s been a relatively recent trend to use C to describe what an FPGA should do and have tools that convert that to an FPGA. However, at least in the case of Xilinx parts, this capability is only available in their newest tool (Vivado), and Vivado doesn’t target the older lower-cost FPGAs that most low-cost development boards use.

[Sleibso] who blogs for Xilinx, has an answer. It turns out you can use the Vivado C compilation tools to generate code for older FPGAs; it just involves a less convenient workflow. Vivado (even the free version) generates unique files that the rest of the tool uses to pick up compiled C code. However, it also generates RTL (Verilog or VHDL) as a by-product, and you can import that into the older ISE tool (which has a perfectly fine free version) and treat it as you would any other RTL files.

There’s an example of using the Vivado tool in the video below. [Sleibso] points out that the video is three years old, and the talk about licensing on the video is out of date. The free tools now including this capability. [Sleibso] talks about using a Spartan 6, but the same split workflow should work with most devices ISE supports.

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[Bunnie] Launches the Novena Open Laptop

Today [Bunnie] is announcing the launch of the Novena Open Laptop. When we first heard he was developing an open source laptop as a hobby project, we hoped we’d see the day where we could have our own. Starting today, you can help crowdfund the project by pre-ordering a Novena.

The Novena is based on the i.MX6Q ARM processor from Freescale, coupled to a Xilinx Spartan 6 FPGA. Combined with the open nature of the project, this creates a lot of possibilities for using the laptop as a hacking tool. It has dual ethernet, for routing or sniffing purposes. USB OTG support lets the laptop act as a USB device, for USB fuzzing and spoofing. There’s even a high speed expansion bus to interface with whatever peripheral you’d like to design.

You can pre-order the Novena in four models. The $500 “just the board” release has no case, but includes all the hardware needed to get up and running. The $1,195 “All-in-One Desktop” model adds a case and screen, and hinges open to reveal the board for easy hacking. Next up is the $1,995 “Laptop” which includes a battery control board and a battery pack. Finally, there’s the $5000 “Heirloom Laptop” featuring a wood and aluminum case and a Thinkpad keyboard.

The hardware design files are already available, so you can drool over them. It will be interesting to see what people start doing with this powerful, open computer once it ships. After the break, check out the launch video.

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Autonomous Quadcopter Fits in the Palm of your Hand

[Horiken Engineering], which is made up of engineering students at the department of aerospace at the University of Tokyo have developed an autonomous quadcopter that requires no external control — and its tiny. By using two cameras and a sonar sensor, the quadcopter is capable of flying by itself due to its ability to process the data from the on-board sensors. To do the complex data processing fast enough to fly, it is using a Cortex-M4 MCU, a Spartan-6 FPGA, and 64MBs of DDRSDRAM. It also has the normal parts of a quadcopter, plus gyros, a 3D printed frame and a 3-axis compass. The following video demonstrates the quadcopter’s tracking ability above a static image (or a way point). The data you see in real-time is only the flight log, as the quadcopter receives no signal — it can only transmit data.

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Pumping 1080p video out of an FPGA


[Hamster] admits this 1080p HDMI hack for an FPGA doesn’t put a signal that’s fully up to specifications. But as you can see in the image above it does output a 1920×1080 image at 60 Hz, which is the size and frequency of full HD video. It falls just short due to some jitter, which may be just fine if this is only being used for early prototyping and will be replaced with a dedicated encoder later in the design process.

Here he’s chosen a Pipistrello board but thinks that any device which has a Spartan 6 chip with the differential pairs connected to an HDMI socket will work. The difficulty of the task comes in serializing four output channels at 1500 Mb/s each. Because of this just coding your logic isn’t going to work. After roughing out the design [Hamster] went back in and chose to manually place some of the components to ensure that data from each channel arrives at the same time.

While you’re messing with HDMI you may also want to give this overlay hack a try.

Conway’s Game of Life in HD

We’re going to have to take [Mike’s] word for it that he built Conway’s Game of Life with high-definition video output. That’s because this screenshot is his only proof and it looks a bit fuzzy to us. But we are interested in the project which used an FPGA to generate a 1080p VGA output of the classic programming challenge.

One of the biggest benefits of using an FPGA for this application is the hardware’s parallel processing ability. For every frame of the game, the area around each living cell must be analyzed to produce the next evolutionary step. Most of the time this means processing all of the pixels in the playing area, which is the case here. [Mike] is using VHDL to program a Papilio Plus which has a Spartan 6 chip on it. He separated his code into the different components when writing about it. This makes it easy to find the chunks relating to the game if that’s what you’re interested in. If you just want to see how he implemented the VGA interface that’s well documented as well.

If you’re not familiar, Conway’s Game of Life has simple rules regarding when a cell will live, die, or be reborn. As [Mike] points out, every programmer should give it a shot at some point. We’ve seen many iterations from the very large to the very small.

Fractal viewer can zoom and enhance like on CSI

This fractal viewer is a great way to get your feet wet with Field-Programmable Gate Arrays. The project will give you some experience working with video output, user input, and a whole bunch of math and memory management. [Hamster] built it using the Papilio Plus board which hosts a Spartan 6 FPGA. This continues his odyssey into the realm of hardware design; part of which we looked at back in December.

The arcade Megawing for the dev board gives him easy access to the controls needed to scroll and zoom on the fractal design. Calculations to generate the shape are being run at 240 MHz, with the VGA output running at 80 MHz. The device has enough horse power and SRAM to show an 800×600 pixel output with a 60 Hz refresh rate.

We really liked the logic diagram that [Hamster] drew up when planning how the calculations would be handled. It’s not overly complex, but it took us a while to conceptualize how everything fits together. It’s certainly an improvement from his last attempt as we couldn’t make heads or tails out of that flow chart.

If you’re just interested in the pretty shapes and colors there’s a demo embedded after the break.

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