A recent trend has been to convert high-level constructs into FPGA code like Verilog or VHDL. Silice goes the other way: it converts very hardware-specific concepts to Verilog and aims to be a more expressive and easier to use language.
Why Silice? The project’s web page enumerates its design goals:
- A clean, simple syntax that clearly exposes the flow of operations and where clock cycles are spent.
- Precise rules regarding flow control (loops, calls) and their clock cycle consumption.
- Familiar hardware constructs such as always blocks, instantiation, expression tracking (wires).
- An optional flow-control oriented design style (automatic FSM generation), that naturally integrates within a design: while, break, subroutines.
- The possibility to easily describe pipelines.
- Automatically takes care of creating flip-flops for variables, with automatic pruning (e.g. const or bindings).
- Generic interfaces and grouped IOs for easy reuse and modular designs.
- Generic circuits that can be instantiated and reused easily.
- Explicit clock domains and reset signals.
- Familiar syntax with both C and Verilog inspired elements.
- Inter-operates with Verilog, allowing to import and reuse existing modules.
- Powerful LUA-based pre-processor.
