Did You Know YoSys Knows VHDL Too?

December 4, 2024 by Elliot Williams 8 Comments

We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write in Verilog or VHDL, your choice. Very cool!

Verilog and VHDL are kind of like the C and ADA of the FPGA world. Verilog will seem familiar to you if you’re used to writing code for computers. For instance, it will turn integer variables into wires that carry the binary values for you. VHDL code looks odd from a software programmer’s perspective because it’s closer to the hardware and strongly typed: an 8-bit integer isn’t the same as eight wires in VHDL. VHDL is a bigger jump if you have software in your brain, but it’s also a lot closer to describing how the hardware actually works.

We learned Verilog, because it’s what Yosys supported. But thanks to GHDL, a VHDL analyzer and synthesizer, and the yosys-ghdl-plugin, you can write your logic in VHDL too. Does this put an end to the FPGA-language holy wars? Thanks, Yosys.

[Michael] points out that this isn’t really news, because the oss-cad-suite install has been doing this for a while now, but like him, it was news to us, and we thought we’d share it with you all.

Want to get started with FPGAs and the open-source toolchain? Our own [Al Williams] wrote up a nice FPGA Boot Camp series that’ll take you from bits to blinking in no time.

Tiny Tapeout 4: A PWM Clone Of Covox Speech Thing

June 21, 2024 by Dave Rowntree 4 Comments

Tiny Tapout is an interesting project, leveraging the power of cloud computing and collaborative purchasing to make the mysterious art of IC design more accessible for hardware hackers. [Yeo Kheng Meng] is one such hacker, and they have produced their very first custom IC for use with their retrocomputing efforts. As they lament, they left it a little late for the shuttle run submission deadline, so they came up with a very simple project with the equivalent behaviour of the Covox Speech Thing, which is just a basic R-2R ladder DAC hanging from a PC parallel port.

The computed gate-level routing of the ASIC layout

The plan was to capture an 8-bit input bus and compare it against a free-running counter. If the input value is larger than the counter, the output goes high; otherwise, it goes low. This produces a PWM waveform representing the input value. Following the digital output with an RC low-pass filter will generate an analogue representation. It’s all very simple stuff. A few details to contend with are specific to Tiny Tapout, such as taking note of the enable and global resets. These are passed down from the chip-level wrapper to indicate when your design has control of the physical IOs and is selected for operation. [Yeo] noticed that the GitHub post-synthesis simulation failed due to not taking note of the reset condition and initialising those pesky flip-flops.

After throwing the design down onto a Mimas A7 Artix 7 FPGA board for a quick test, data sent from a parallel port-connected PC popped out as a PWM waveform as expected, and some test audio could be played. Whilst it may be true that you don’t have to prototype on an FPGA, and some would argue that it’s a lot of extra effort for many cases, without a good quality graphical simulation and robust testbench, you’re practically working blind. And that’s not how working chips get made.

If you want to read into Tiny Tapeout some more, then we’ve a quick guide for that. Or, perhaps hear it direct from the team instead?

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What’s The Difference Between Tang 9K And 20K (It Isn’t 11…)

June 6, 2024 by Al Williams 18 Comments

[Grug Huhler] has been working with the Tang Nano 9K FPGA board. They are inexpensive, and he noticed there is a 20K version, so he picked one up. Of course, you’d expect the 20K board has a different FPGA with more gates than the 9K, but there are also a number of differences in the host board. [Grug] was kind enough to document the differences in the video below.

In addition to the differences, there’s a good demo of the boards hosting a system-on-chip design. The little DIP package is handy for breadboarding. All of the 20K pins are 3.3 V, according to the documentation. The 9K does have some 1.8 V pins. There are more external devices on the 20K board but that eats up more uncommitted pins. Depending on your design, that may or may not be a problem.

We keep meaning to pick some of these up to play with. The Verilog is easy enough, and the tools look adequate. If you need a refresher on Verilog, we have a boot camp for you that would probably port easily enough to the Tang system. We’ve been following [Grug’s] work on these chips lately, and you should, too.

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The 6809 Lives On In An FPGA

May 28, 2024 by Al Williams 38 Comments

At one point, the Motorola 6809 seemed like a great CPU. At the time it was a modern 8-bit CPU and was capable of hosting position-independent code and re-entrant code. Sure, it was pricey back in 1981 (about four times the price of a Z80), but it did boast many features. However, the price probably prevented it from being in more computers. There were a handful, including the Radio Shack Color Computer, but for the most part, the cheaper Z80 and the even cheaper 6502 ruled the roost. Thanks to the [turbo9team], however, you can now host one of these CPUs — maybe even a better version — in an FPGA using Verilog.

The CPU may be old-fashioned on the outside, but inside, it is a pipeline architecture with a standard Wishbone bus to incorporate other cores to add peripherals. The GitHub page explains that while the 6809 is technically CISC, it’s so simple that it’s possible to translate to a RISC-like architecture internally. There are also a few enhanced instructions not present on the 6809.

In addition to the source code, you’ll find a thesis and some presentations about the CPU in the repository. While the 6809 might not be the most modern choice, it has the advantage of having plenty of development tools available and is easy enough to learn. Code for the 6800 should run on it, too.

Even using through-hole parts, you can make a 6809 computer fit in a tiny space.You can also break out a breadboard.

Manta: An Open On-FPGA Debug Interface

May 1, 2024 by Arya Voronova 30 Comments

We always can use more tools for FPGA debugging, and the Manta project by [Fischer Moseley] delivers without a shadow of a doubt. Manta lets you add a debug and data transfer channel between your computer and your FPGA, that you can easily access with helpfully included Python libraries.

With just a short configuration file as input, it gives you cores you add into your FPGA design, tapping the signals of interest as an FPGA-embedded logic analyzer, interacting with registers, and even letting you quickly transfer tons of data if you so desire.

Manta is easy to install, is developer-friendly, has been designed in Amaranth, and is fully open source as you would expect. At the moment, Manta supports both UART and Ethernet interfaces for data transfer. As for embedding the Manta cores into your project, they can be exported to both Amaranth and Verilog. You should check out the documentation website — it contains everything you might want to know to get started quick.

The Manta project has started out as our hacker’s MIT thesis, and we’re happy that we can cover it for you all. FPGA-embedded logic analyzers are a fascinating and much-needed tool, and we’ve had our own [Al Williams] tell you about his on-FPGA logic analysis journey!

Do We Need A New Hardware Description Language?

March 15, 2024 by Al Williams 20 Comments

When you think about hardware description languages, you probably think of Verilog or VHDL. There are others, of course, but those are the two elephants in the room. Do we need another one? [Veryl-lang] thinks so. The Veryl language is sort of Verilog meets Rust. What makes Veryl interesting is that it transpiles to normal SystemVerilog, so it will — probably — work with your existing tool chains.

That means you can define your logic Veryl, have it output SystemVerilog, and then use that Verilog in your vendor’s (or an open source) Verilog tool. The output is supposed to be human-readable Verilog, too, so you don’t have to transport opaque blocks of gibberish.

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QSPICE Picks Up Where LTSpice Left Us

August 25, 2023 by Dave Rowntree 23 Comments

[Mike Engelhardt] is a name that should be very familiar to the hardcore electronics nerd. [Mike] is the developer responsible for LTSpice, which is quite likely the most widely used spice-compatible simulator in the free software domain. When you move away from digital electronics and the comfort of software with its helpful IDEs and toolchains, and dip a wary toe into the murky grey waters of analog or power electronics, LTSpice is your best friend. And, like all best friends, it’s a bit quirky, but it always has your back. Sadly, LTSpice development seems to have stalled some years ago, but luckily for us [Mike] has been busy on the successor, QSpice, under the watchful eye of Qorvo.

It does look in its early stages, but from a useability point of view, it’s much improved over LTSpice. Performance is excellent (based on this scribe’s limited testing while mobile.) Gone (thankfully!) is the uncommon verb-noun usage paradigm — replaced with a more usual cut-n-paste flow. Visually it still kind of looks like LTspice in places, but nicer with a clear and uncluttered design that gets straight to the point. Internally, the simulation engine has improved in speed and accuracy, as well as adding native support for modern semiconductor types, such as wide bandgap materials like SiC. Noted is that this updated software has a particular emphasis on power integrity and noise analysis, which are sticky problems that have a big impact on modern high-power systems.

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