Building A Custom Zynq-7000 SoC Development Board From The Ground Up

April 20, 2025 by John Elliot V 7 Comments

In this series of 23 YouTube videos [Rich] puts the AMD Zynq-7000 SoC through its paces by building a development board from the ground up to host it along with its peripherals. The Zynq is part FPGA and part CPU, and while it has been around for a while, we don’t see nearly as many projects about it as we’d like.

[Rich] covers everything from the power system to HDMI, USB, DDR RAM, and everything in between. By the end, he’s able to boot PetaLinux.

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A slide from a talk about Spade language with a diagram about how it fits in with Verilog, VHDL, and HLS.

The Spade Hardware Description Language

April 13, 2025 by John Elliot V 15 Comments

Spade is an open-source hardware description language (HDL) developed at Linköping University, Sweden.

Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to define hardware which can be rendered in silicon. Hardware defined in HDLs might look like software, but actually it’s not software, it’s hardware description. This hardware can be realized myriad ways including in an FPGA or with an ASIC.

You have probably heard that your CPU processes instructions in a pipeline. Spade has first-class support for such pipelines. This means that design activities such as re-timing and re-pipelining are much easier than in other HDLs where the designer has to implement these by hand. (Note: backward justification is NP-hard, we’re not sure how Spade supports this, if it does at all. If you know please enlighten us in the comments!)

Spade implements a type system for strong and static typing inspired by the Rust programming language and can do type inference. It supports pattern matching such as you might see in a typical functional programming language. It boasts having user-friendly and helpful error messages and tooling.

Spade is a work in progress so please expect missing features and breaking changes. The documentation is in The Spade Book. If you’re interested you can follow development on GitLab or Discord.

So now that you know about the Spade language, are you planning to take it for a spin? You will find plenty of Verilog/VHDL designs at Hackaday which you could re-implement using Spade, such as an easy one like Breathing LED Done With Raw Logic Synthesized From A Verilog Design (see benchmarks) or a much more challenging one like Game Boy Recreated In Verilog. If you give Spade a go we’d love to see what you come up with!

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Reconfigurable FPGA For Single Photon Measurements

March 30, 2025 by Heidi Ulrich 6 Comments

Detecting single photons can be seen as the backbone of cutting-edge applications like LiDAR, medical imaging, and secure optical communication. Miss one, and critical information could be lost forever. That’s where FPGA-based instrumentation comes in, delivering picosecond-level precision with zero dead time. If you are intrigued, consider sitting in on the 1-hour webinar that [Dr. Jason Ball], engineer at Liquid Instruments, will host on April 15th. You can read the announcement here.

Before you sign up and move on, we’ll peek into a bit of the matter upfront. The power lies in the hardware’s flexibility and speed. It has the ability to timestamp every photon event with a staggering 10 ps resolution. That’s comparable to measuring the time it takes light to travel just a few millimeters. Unlike traditional photon counters that choke on high event rates, this FPGA-based setup is reconfigurable, tracking up to four events in parallel without missing a beat. From Hanbury-Brown-Twiss experiments to decoding pulse-position modulated (PPM) data, it’s an all-in-one toolkit for photon wranglers. [Jason] will go deeper into the subject and do a few live experiments.

Measuring single photons can be achieved with photomultipliers as well. If exploring the possibilities of FPGA’s is more your thing, consider reading this article.

Acoustic Levitation Gets Insects Ready For Their Close-Up

March 22, 2025 by Tom Nardi 6 Comments

The average Hackaday reader is likely at least familiar with acoustic levitation — a technique by which carefully arranged ultrasonic transducers can be used to suspend an object in the air indefinitely. It’s a neat trick, the sort of thing that drives them wild at science fairs, but as the technique only works on exceptionally small and light objects it would seem to have little practical use.

That is, unless, you happen to be interested in exceptionally small and light objects. A paper titled Automated Photogrammetric Close-Range Imaging System for Small Invertebrates Using Acoustic Levitation describes a fascinating device which allows the researchers to image insects in what’s essentially a weightless environment.

With the delicate specimens suspended in front of the lens, there’s no background to worry about and they can be perfectly lit from all angles. What’s more, with careful control of the ultrasonic transducers, it’s possible to control the rotation of the target — allowing researchers to produce 3D scans of the insects using just one camera.

There isn’t a whole lot of technical detail on the device itself, other than the fact that spherical chamber has a radius of 60 mm and is fitted with 96 Murata MA40S4R/S transducers operating at 40 kHz. The paper notes that early attempts to control the transducer array with a Arduino Mega failed, and that the team had to switch over to a FPGA. With their current signal generator stage, the researchers are able to rotate the specimen by 5° angles.

Interested in learning more about acoustic levitation? University of Bristol research scientist Asier Marzo gave a talk on the subject at Hackaday Belgrade in 2018 that you won’t want to miss.

A New 8-bit CPU For C

February 21, 2025 by Al Williams 60 Comments

It is easy to port C compilers to architectures that look like old minicomputers or bigger CPUs. However, as the authors of the Small Device C Compiler (SDCC) found, pushing C into a typical 8-bit CPU is challenging. Lessons learned from SDCC inspired a new 8-bit architecture, F8. This isn’t just a theoretical architecture. You can find an example Verilog implementation in the SDDC project and on GitHub. The name choice may turn out to be unfortunate as there was an F8 CPU from Fairchild back in the 1970s that apparently few people remember.

In the video from FOSDEM 2025, [Phillip Krause] provides a nice overview of the how and why of F8. While it might seem odd to create a new 8-bit CPU when you can get bigger CPUs for pennies, you have to consider that 8-bit machines are more than enough for many jobs, and if you can squeeze one into an FPGA, it might be a good choice as opposed to having to get a bigger FPGA to hold your design and a 32-bit CPU.

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T1 Is A RISC-V Cray

February 6, 2025 by Al Williams 16 Comments

The crux of most supercomputers is the ability to operate on many pieces of data at once — something video cards are good at, too. Enter T1 (short for Torrent-1), a RISC-V vector inspired by the Cray X1 vector machine.

T1 has support for features, including lanes and chaining. The chip contains a version of the Rocket Core for scalar operations, but there’s no official support for using it. The project claims you could easily replace that core with any other RISC-V CPU IP.

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High Performance RISC-V

January 3, 2025 by Al Williams 12 Comments

From the Institute of Computing Technology division of the Chinese Academy of Sciences and Peng Cheng Laboratory comes a high-performance and well-documented RISC-V core called XiangShan.

In the Git repository, you’ll find several branches including at least two stable branches: Yanqihu and Nanhu. The currently developed architecture, Kunminghu, is impressive, with a sophisticated instruction fetch unit, a reorder buffer, and a register renaming scheme.

The point of these types of circuits in a CPU is to allow multiple instructions to process at once. This also implies that instructions can be executed out of order. A cursory glance didn’t show any branch prediction logic, but that may be a limitation of the documentation. If there isn’t one, that would be an interesting thing to add in a fork if you are looking for a project.

On the computing side, the processor contains an integer block, a floating point unit, and a vector processor. Clearly, this isn’t a toy processor and has the capability to compete with serious modern CPUs.

There is a separate GitHub for documentation. It looks like they try to keep documentation in both Mandarin and English. You can also find some of the academic papers about the architecture there, too.

We love CPU design, and this is an interesting chance to contribute to an open CPU while there are still interesting things to do. If you need to start with something easier, plenty of small CPUs exist for educational purposes.