Hackaday Prize Entry: HOMER, A 2D GPU For Microcontrollers

Just about the hardest thing you’ll ever do with a microcontroller is video. The timing must be precise, and even low-resolution video requires relatively large amounts of memory, something microcontrollers don’t generally have a lot of. HDMI? That’s getting into microcontroller wizard territory.

Despite these limitations, [monnoliv] is working on a GPU for microcontrollers. It outputs 1280×720 over HDMI, has a 24 bit palette, and 2D hardware acceleration.

It’s a very interesting project; usually, if you want graphics and a display in a project, you’re looking at a Linux system, and all the binary blobs and closed source drivers that come with that. [monnoliv]’s HOMER video card doesn’t need Linux, and it doesn’t need a very high-powered microcontroller. It’s just a simple SPI device with a bunch of memory and an FPGA that turns the most minimal microcontroller into a machine that can output full HD graphics.

This isn’t the only open source graphics card for microcontrollers in the Hackaday Prize; just a few days ago, we saw VGAtonic, another SPI-controlled video card for microcontrollers, this time outputting VGA instead of HDMI. Both are excellent projects, and if either makes it into production, they’ll both be cheap: under $100 for both of them. Just the thing if you want to play around with high-resolution video without resorting to Linux.


The 2015 Hackaday Prize is sponsored by:

Two New Dev Boards That Won’t Make Your Wallet Hurt-So-Good

If you’ve been keeping up with the hobbyist FPGA community, you’ll recognize the DE0 Nano as “that small form-factor FPGA” with a deep history of projects from Oldland cpu cores to synthesizable Parallax Propeller processors. After more than four years in the field though, it’s about time for a reboot.

Its successor, the DE0 Nano SoC, is a complete redesign from multiples perspectives while doing it’s best to preserve the bite-size form factor and price that made the first model so appealing. First, the dev board boasts a Cyclone V with 40,000 logical elements (up from the DE0’s 22K) and an integrated dual-core Arm Cortex A9 Processor. The PCB layout also brings us  3.3V Arduino shield compatibility via female headers, 1 Gig of external DDR3 SDRAM and gigabit ethernet support via two onboard ASICs to handle the protocol. The folks at Terasic also seem to be tipping their hats towards the “Duino-Pi” hobbyist community, given that they’ve kindly provided both Linux and Arduino images to get you started a few steps above your classic finite-state machines and everyday combinational logic.

And while the new SoC model sports a slightly larger form factor at 68.59mm x 96mm (as opposed to the original’s 49mm x 75.2mm), we’d say it’s a small price to pay in footprint for a whirlwind of new possibilities on the logic level. The board hits online shelves now at a respectable $100.

Next, as a heads-up, the aforementioned Arduino Zero finally makes it’s release on June 15. If you’ve ever considered taking the leap from an 8-bit to a 32-bit processor without having to hassle through the setup of an ARM toolchain, now might be a great time to get started.

via [the Arduino Blog]

Hackaday Prize Entry: Very, Very Small Logic

Despite the existence of FPGAs and CPLDs, there’s still a necessity for very small programmable logic devices. GALs, PALs, and other old tech just won’t cut it, though, and so we are left with a new generation of programmable devices that aren’t microcontrollers or CPUs. The GreenPAC from Silego fill this niche quite nicely, with the ability to implement counters, ADCs, logic glue, level shifting, and comparators in a single chip. For any homebrew electronics tinkerer, these devices have one very obvious problem: they’re really, really small. The smallest GreenPAC device has 12 pins stuffed into a 1.6 x 1.6mm QFN package. You’re not hand soldering this thing.

For [Nick Johnson]’s Hackaday Prize entry, he’s taking these small programmable logic chips and making it easy to create your own custom ICs. Basically, it’s a breakout board for GreenPAC devices that stuffs these tiny chips onto a much more reasonable DIP package.

Breakouts aren’t enough, and to program these small chips, [Nick] is also building a board based on an ARM microcontroller. With USB input, a way to generate the 7.5V used for programming, and a breadboard friendly format, this programmer will tell these tiny chips what to do.

Not many people are building stuff with PALs and GALs anymore, but there are still a lot of work that can be done with small programmable chips. There’s certainly a place for tiny programmable logic chips like this, and anything that gets them in to the hands of more people is okay in our book.


The 2015 Hackaday Prize is sponsored by:

Solving Rubik’s Cube With An FPGA

For their final project for ECE 5760 at Cornell, [Alex], [Sungjoon], and [Rameez] are solving Rubik’s Cubes. They’re doing it with an FPGA, with homebrew robot arms to twist and turn a rainbow cube into the correct position.

First, the mechanical portion of the build. The team are using a system of three robot arms positioned on the left, right, and back faces of the cube relative to a camera. When a cube is placed in the jaws of this robot, the NTSC camera data is fed into an FPGA, where a Nios II soft core handles the actual detection of the cube faces, the solver algorithm, and the controller to send servo commands to the robot arms.

The algorithm used for solving the cube is CFOP – solve the white cross, the white corners, the middle layer, the top face, and finally the entire cube. In practice, the robot ended up taking between 60-70 moves. This is not the most efficient algorithm; the Thistethwaite algorithm only requires 52 moves. There’s a reason for this apparent inefficiency – the Thistlethwaite algorithm requires large look-up tables.

Once the cube is scanned and the correct moves are computed, the soft core in sends commands out through the FPGA’s GPIO pins. Each cube can be solved in under three minutes after it has been scanned, but the team ran into problems with scanning accuracy. It’s a problem that can be fixed with the right lighting setup and better aberrant cubie detection, and a great final project using FPGAs.

Video demo below.

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Intel Buys Altera For $16.7 Billion

Intel, CPU manufacturer we all know and love, will buy Altera, makers of fine FPGAs, for $16.7 Billion.

While most of the news about this deal focuses on the future of FPGAs in the datacenter, getting Altera IP into Intel fab houses is equally interesting. Intel is the current king of putting transistors on a piece of silicon, and Intel’s ability to put a massive amount of transistors on a chip means FPGAs will become even more capable – more gates, more blocks, and more memory. The most capable Altera FPGAs are being made with a 28nm process; Intel could theoretically double the number of gates with the 14nm process used on the new Broadwell CPUs. There is most likely someone at Xilinx tearing their hair out right now, chain-smoking next to a pot of coffee.

News of this buy out comes about a week after Avago bought Broadcom in the biggest semiconductor deal ever, and a few months after NXP and Freescale merged. Cash Rules Everything Around Semiconductors, it seems.

An Open Source Toolchain For iCE40 FPGAs

FPGAs are great, but open source they are not. All the players in FPGA land have their own proprietary tools for creating bitstream files, and synthesizing the HDL of your choice for any FPGA usually means agreeing to terms and conditions that nobody reads.

After months of work, and based on the previous work of [Clifford Wolf] and [Mathias Lasser], [Cotton Seed] has released a fully open source Verilog to bitstream development tool chain for the Lattice iCE40LP with support for more devices in the works.

Last March, we saw the reverse engineering of the Lattice ICE40 bitstream, but this is a far cry from a robust, mature development platform. Along with Yosys, also written by [Clifford Wolf] it’s relatively simple to go from Verilog to an FPGA that runs your own code.

Video demo below, and there’s a ton of documentation over on the Project IceStorm project page. You can pick up the relevant dev board for about $22 as well.

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Dancing Mandelbrot Set on a FPGA

This FPGA based build creates an interesting display which reacts to music. [Wancheng’s] Dancing Mandelbrot Set uses an FPGA and some math to generate a controllable fractal display.

The build produces a Mandelbrot Set with colours that are modified by an audio input. The Terasic DE2-115 development board, which hosts a Cyclone IV FPGA, provides all the IO and processing. On the input side, UART or an IR remote can be used to zoom in and out on the display. An audio input maps to the color control, and a VGA output allows for the result to be displayed in real time.

Dancing Mandelbrot Block DiagramOn the FPGA, a custom calculation engine, running at up to 150 MHz, does the math to generate the fractal. A Fast Fourier transform decomposes the audio input into frequencies, which are used to control the colors of the output image.

This build is best explained by watching, so check out the video after the break.

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