Papilio Duo: FPGA, Logic Analyzer, Debugger, and Arduino Compatible

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It’s been a while since we’ve seen some new boards that combine an FPGA and an Arduino, so naturally the state of the art is a little bit behind. The latest from [Jack Gassett], the Papilio Duo, aims to change that by addressing all the complaints of the original Papilio and adding some neat, modern features that you would expect on a board designed in 2014.

On board the Duo is an ATMega32u4, the same chip used in the Arduino Leonardo, allowing for easy integration with your standard Arduino projects. The top of the board is where the real money is. There’s a Spartan 6 FPGA with 9k logic cells, enough to run emulate some of the classic computers of yore, including the famous SID chip, Yamaha YM2149, and the Atari POKEY (!).  With host and device USB, 512k or 2M of SRAM, and an ADC on the FPGA inputs, this board should be able to handle just about everything you would want to throw at it. There’s even a breakout for HDMI on the bottom.

There are a few interesting software features of the Duo, including a full debugger for the ATMega chip, thanks to an emulated Atmel JTAG ICE MKII. Yes, an Arduino-compatible board finally has a real debugger. The FPGA can also implement a 32 channel logic analyzer, making this not only an extremely powerful dev board, but also a useful tool to keep around the workbench.

Augmented Reality with an FPGA

 

bruceinabox

 

[Julie Wang] has created an augmented reality system on a Field Programmable Gate Array (FPGA). Augmented reality is nothing new – heck, these days even your tablet can do it. [Julie] has taken a slightly different approach though. She’s not using a processor at all. Her entire system, from capture, to image processing, to VGA signal output, is all instantiated in a FPGA.

Using the system is as simple as holding up a green square of cardboard. Viewing the world through an old camcorder, [Julie's] project detects and tracks the green square. It then adds a 3D image of Cornell’s McGraw Tower on top of the green. The tower moves with the cardboard, appearing to be there. [Julie] injected a bit of humor into the project through the option of substituting the tower for an image of her professor, [Bruce Land].

[Julie] started with an NTSC video signal. The video is captured by a DE2-115 board with an Altera Cyclone IV FPGA. Once the signal was inside the FPGA, [Julie's] code performs a median filter. A color detector finds an area of green pixels which are passed to a corner follower and corner median filter. The tower or Bruce images are loaded from ROM and overlaid on the video stream, which is then output via VGA.

The amazing part is that there is no microprocessor involved in any of the processing. Logic and state machines control the show. Great work [Julie], we hope [Bruce] gives you an A!

[Read more...]

Phenox: Wherein Quadcopters Get FPGAs

quad

The computing power inside a quadcopter is enough to read a few gyros and accelerometers, do some math, and figure out how much power to send to the motors. What if a quadcopter had immensely more computing power, and enough peripherals to do something cool? That’s what Phenox has done with a micro quad that is able to run Linux.

Phenox looks like any other micro quad, but under the hood things get a lot more interesting. Instead of the usual microcontroller-based control system, the Phenox features a ZINQ-7000 System on Chip, featuring an ARM core with an FPGA and a little bit of DDR3 memory. This allows the quad to run Linux, made even more interesting by the addition of two cameras (one forward facing, one down facing), a microphone, an IMU, and a range sensor. Basically, if you want a robotic pet that can hover, you wouldn’t do bad by starting with a Phenox.

The folks behind Phenox are putting up a Kickstarter tomorrow. No word on how much a base Phenox will run you, but it’ll probably be a little bit more than the cheap quads you can pick up from the usual Chinese retailers.

Videos below.

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[Bunnie]‘s Laptop Gets A 900MHz Scope Addon

Scope

Now that [Bunnie]‘s open hardware laptop – the Novena – is wrapping up its crowdfunding campaign, it only makes sense that development around the Novena project would move over to the more interesting aspects of a completely hackable laptop. The Novena has a huge FPGA on board, with 2 Gbit of very fast memory hanging off it. Also, every single signal pin of the FPGA is broken out on high-speed connectors, making for some very, very interesting possible add-on boards. [Bunnie] has always wanted a portable, high-end oscilloscope to carry with him, and with the new oscope module, he has something that blows out of the water every scope priced below a thousand dollars.

The oscilloscope module [Bunnie] is working on has either two 8-bit channels at 1 GSPS or one 8-bit channel at 2 GSPS with an analog bandwidth of up to 900MHz. The module also has 10 digital channels, so if you need a logic analyzer, there you go.

Being a fairly high-end scope, the hardest part of engineering this scope is the probes. The probes for fast, high-end scopes cost hundreds of dollars by themselves, so [Bunnie] looked for a clean-sheet redesign of the lowly oscope probe. To connect the probe to the module, [Bunnie] realized a SATA cable would be a great solution; they’re high bandwidth, support signals in the GHz range, and are rated for thousands of insertions. These active probes can be combined with a number of front ends for application specific probes – digital probes, ones for power signature analysis, and ones for capturing signals across small loops of wire.

The module itself isn’t quite ready for production yet, but by the time the Novena crowdfunding campaign starts shipping, [Bunnie] will probably be working on the next add-on module for his crazy awesome laptop.

 

A Z80 Retro Microcomputer for the Papilio Pro FPGA Board

z80

[Will] wrote a 128MHz Z80-based retro microcomputer which runs on a Papilio Pro board. For those who don’t know, the latter is built around a Spartan-6 LX9 FPGA so you may imagine that much work was required to implement all the computer features in VHDL. The T80 CPU core was taken from opencores, the SDRAM controller was imported from Mike Field’s work but [Will] implemented several additional functions on his own:

- a 4KB paged Memory Management Unit to translate the 16-bit (64KB) logical address space into a 26-bit (64MB) physical address space.

- a 16KB direct mapped cache to hide the SDRAM latency, using the FPGA internal block RAM

- a UART interface for external communications

He also ported CP/M-2.2, MP/M-II and UZI (a UNIX system) to the computer. His project is completely open-source and all the source code can be downloaded at the end of [Will]‘s write up.

Thanks [hamster] for the tip.

BeagleBone Black and FPGA Driven LED Wall

LED Wall

 

This is 6,144 RGB LEDs being controlled by a BeagleBone Black and a FPGA. This gives the display 12 bit color and a refresh rate of 200 Hz. [Glen]‘s 6 panel LED wall uses the BeagleBone Black to generate the image, and the LogiBone FPGA board for high speed IO.

[Glen] started off with a single 32 x 32 RGB LED panel, and wrote a detailed tutorial on how that build works. The LED panels used for this project have built in drivers, but they cannot do PWM. To control color, the entire panel must be updated at high speed.

The BeagleBone’s IO isn’t fast enough for this, so a Xilinx Spartan 6 LX9 FPGA takes care of the high speed signaling. The image is loaded into the FPGA’s Block RAM by the BeagleBone, and the FPGA takes care of the rest. The LogiBone maps the FPGA’s address space into the CPU’s address space, which allows for high speed transfers.

If you want to drive this many LEDs, you’ll need to look beyond the Arduino. [Glen]‘s work provides a great starting point, and all of the source is available on Github.

[Thanks to Jonathan for the tip]

CPLD Tutorial: Learn Programmable Logic the Easy Way

739px-Altera_MAX_7128_2500_gate_CPLD

The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. Programmable logic devices are one of the most versatile hardware building blocks available to hackers. They also can have a steep learning curve. Cheap Field Programmable Gate Arrays (FPGA) are plentiful, but can have intricate power requirements. Most modern programmable logic designs are created in a Hardware Description Language (HDL) such as VHDL or Verilog. Now you’ve got a new type of device, a new language, an entirely new programming paradigm, and a complex IDE to learn all at once. It’s no wonder FPGAs have sent more than one beginner running for the hills.

The tutorial cuts the learning curve down in several ways. [Carl] is using Complex Programmable Logic Devices (CPLD). At the 40,000 foot level, CPLDs and FPGAs do the same thing – they act as re-configurable logic. FPGAs generally do not store their configuration – it has to be loaded from an external FLASH, EEPROM, or connected processor. CPLDs do store their configuration, so they’re ready as soon as they power up. As a general rule, FPGAs contain more configurable logic than CPLDs. This allows for larger designs to be instantiated with FPGAs. Don’t knock CPLDs though. CPLDs have plenty of room for big designs, like generating VGA signals.

[Carl] also is designing with schematic capture in his tutorial. With the schematic capture method, digital logic schematics are drawn just as they would be in Eagle or KiCad. This is generally considered an “old school” method of design capture. A few lines of VHDL or Verilog code can replace some rather complex schematics. [Carl's] simple designs don’t need that sort of power though. Going the schematic capture route eliminates the need to learn VHDL or Verilog.

[Carl's] tutorial starts with installing Altera’s Quartus II software. He then takes the student through the “hardware hello world” – blinking an LED.  By the time the tutorial is done, the user will learn how to create a 4 bit adder and a 4 bit subtractor. With all that under your belt, you’re ready to jump into big designs – like building a retrocomputer.

[Image via Wikimedia Commons]

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