cpu

127 Articles

You Know You Can Do That With A 555

August 10, 2017 by 34 Comments

Hardly a week goes by that we don’t post a project where at least one commenter will lament that the hacker could have just used a 555. [Peter Monta] clearly gets that point of view. For a 555 design contest, he created both digital logic gates and an op amp, all using 555 chips. We can’t quite imagine the post apocalyptic world where the only surviving electronic components are 555 chips, but if that day were to come, [Peter] is your guy.

Using the internal structure of the 555, [Peter] formed a basic logic gate, an inverter, latches, and more. He also composed things like counters and seven-segment decoders. He had a very simple 4-bit CPU design in Verilog that he was going to attempt until he realized it would map into almost 400 chips (half of that if you’d use a dual 555, but still). If you built this successfully, we would probably post it, by the way.  You can see a video of the digital logic counter, below.

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Find Instructions Hidden In Your CPU

July 30, 2017 by 79 Comments

There was a time when owning a computer meant you probably knew most or all of the instructions it could execute. Your modern PC, though, has a lot of instructions, many of them meant for specialized operating system, encryption, or digital signal processing features.

There are known undocumented instructions in a lot of x86-class CPUs, too. What’s more, these days your x86 CPU might really be a virtual machine running on a different processor, or your CPU could have a defect or a bug. Maybe you want to run sandsifter–a program that searches for erroneous or undocumented instructions. Who knows what is lurking in your CPU?

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Virtual CPU Stays On Script

July 22, 2017 by 16 Comments

Some will see it as a great thing, and others as an example of how JavaScript is being abused daily, but [Francis Stokes] decided to design his own CPU architecture and implemented a virtual version of it using JavaScript. The CPU is a 16-bit affair and has a simplified assembly language. The code is on GitHub, but the real value is [Francis’] exposition of the design in the original post.

While discussing the design, [Francis] reveals his first pass at the instruction set, discussed what he found wrong about it, and then reveals the final set composed of real instructions and some macros to handle other common cases.

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VexRiscv: A Modular RISC-V Implementation For FPGA

July 21, 2017 by 16 Comments

Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.

SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.

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Simulating The Learn-by-Fixing CPU

May 12, 2017 by 24 Comments

Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool called EDA Playground. This time, I’ll take you through the code details and how to run the simulation.

You’ll want to refer to the previous post if you didn’t read it already. The diagrams and tables give a high-level overview that will help you understand the files discussed in this post.

If you wanted to actually program this on a real FPGA, you’d have a little work to do. The memory and register initialization is done in a way that works fine for simulation, but wouldn’t work on a real FPGA. Anyway, let’s get started!

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Learn By Fixing: Another Verilog CPU

May 5, 2017 by 17 Comments

Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.

The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. However, what was worse is one of the modules needed to get it to work was missing! You might argue it was an exercise left to the reader, but it probably should have been pointed out that way.

At first, I was ready to delete the bookmark and move on. Then I decided that the process of fixing this design and doing a little analysis on it might actually be more instructive than just studying a fully working design. So I decided to share my fix with you and look inside the architecture a bit more. On top of that, I’ll show you how to get the thing to run in an online simulator so you can experiment with no software installation. Of course, if you are comfortable with a Verilog toolchain (like the ones from Xilinx or Altera, or even free ones like Icarus or CVer) you should have no problem making that work, either. This time I’ll focus on how the CPU works and next time I’ll show you how to simulate it with some free tools. Continue reading “Learn By Fixing: Another Verilog CPU” →

An 8-Bit Transport Triggered Architecture CPU In TTL

April 21, 2017 by 37 Comments

When we are introduced to the internals of a microprocessor, it is most likely that we will be shown something like one of the first generation of 8-bit CPUs from the 1970s. There will be the familiar group of registers and counters, an arithmetic and logic unit (ALU), and an instruction decoder with associated control logic. A complex instruction set causes the decoder to marshal registers and ALU to perform all the various functions in the right order. CPUs may have moved on in many ways since the 1970s, but the block diagram of an 8080 or similar still provides a basic grounding for the beginner.

So when we tell you about another home-made CPU using TTL logic chips, you might expect it to follow this well-worn path. Fortunately though the hardware hacking community is always capable of springing surprises upon us, and [Szoftveres] has done just that with his design. It’s a one-instruction-set machine following a transport triggered architecture, and that means it deviates sharply from the conventional architecture described above. Each instruction is a move between the different physical functions of the processor, and computation is achieved by the physical functions working on the data as it is moved into them and presenting the result on their outputs ready to be moved elsewhere. The result is a computer that is in its own way beautifully simple, though at the expense of some inflexibility and lack of some hardware functions we take for granted in more conventional processors.

This machine has been built on a piece of stripboard, and has an accompanying board with display, keypad, and a modem. There is a small board based upon an ATmega8 microcontroller which performs the function of fast program loading, and can be removed once the code is loaded. Software can be written in a C-like language anc compiled using the compiler in his GitHub repository, and he has produced a YouTube video of the machine in operation. This project is well worth reading through in-depth, for its introduction to this slightly unusual architecture.

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