Tang FPGA boards are affordable, and [nand2mario] has been trying to get an x86 core running on one for a while. Looks like it finally worked out, as there is an early version of the ao486 design on a Tang FPGA board using a Gowin device. That core’s available on the MiSTer platform, which emulates games using an Altera Cyclone device.
Of course, porting something substantial between FPGA architectures is not trivial. In addition, [nand2mario] made some changes. The original core uses DDR3 memory, but for the Tang and the 486, SDRAM makes more sense. The only problem is that the Tang’s SDRAM is 16 bits wide, which would imply you need two cycles per 32-bit access. To mitigate this, the memory system runs at twice the main clock frequency. Of course, that’s kind of double data rate, but not in the same way as DDR memory.
Does the in 65F02 “F” stand for “fast” or “FPGA”? [Jurgen] doesn’t know, but his drop-in replacement board for the 6502 and 65c02 is out there and open source, whatever you want it to stand for.
The “f” could easily be both, since at 100 MHz, the 65f02 is blazing fast by 6502 standards–literally 100 times the speed of the first chips from MOS. That speed comes from the use of a Spartan 6 FPGA core to implement the 6502 logic; making the “f” stand for “FPGA” makes sense, given that the CMOS version of the chip was dubbed the 65c02. The 65f02 is a tiny PCB containing the FPGA and all associated hardware that shares the footprint of a DIP-40 package, making it a drop-in replacement. A really fast drop-in replacement.
You might be thinking that that’s insane, and that (for example) the memory on an Apple ][ could never run at 100 MHz and so you won’t get the gains. This is both true, and accounted for: the 65F02 has an internal RAM “cache” that it mirrors to external memory at a rate the bus can handle. When memory addresses known to interact with peripherals change, the 65f02 slows down to match for “real time” operations.
The USB adapter board for programming is a great touch.
Because of this the memory map of the external machine matters; [Jurgen] has tested the Commodore PET and Apple ][, along with a plethora of German chess computers, but, alas, this chip is not currently compatible with the Commodore 64, Atari 400/800 or BBC Micro (or at least not tested). The project is open source, however, so you might be able to help [Jurgen] change that.
We admit this project isn’t totally new– indeed, it looks like [Jurgen]’s last update was in 2024– but a fast 6502 is just as obsolete today as it was when [Jurgen] started work in 2020. That’s why when [Stephen Walters] sent us the tip (via electronics-lab), we just had to cover it, especially considering the 6502’s golden jubilee.
If you’ve never used a PDP-11 before it’s probably because you simply weren’t around in the 70s and 80s. Although they started as expensive machines only in research labs and industry, they eventually became much more accessible. They’re a bit of a landmark in computing history, too, being largely responsible for the development of things like UNIX and the C programming language. [ryomuk] is using an FPGA in combination with an original DEC J-11 to bring us a new take on this machine. (Google Translate from Japanese)
The FPGA used in this build is a Tang Nano 20k, notable for its relatively low cost. The FPGA emulates the memory system and UART of a PDP-11 system down to the instruction set, while the original, unmodified DEC chip is left to its own devices. After some initial testing [ryomuk] built a PC11 paper tape emulator to ensure the system was working which runs a version of BASIC from the era. The next thing up was to emulate some disk drives and co-processors so that the machine can run the first version of UNIX.
[ryomuk] also developed a PCB for the DEC microprocessor and the FPGA to sit on together, and it includes all of the jumpers and wiring needed to allow the computer to run UNIX, as well as handling other miscellaneous tasks like power. It’s an interesting build that gets to the heart of the early days of computer science. PDP-11 computers did eventually get smaller and more accessible, and if you want to build a modern version this build fits a complete system into an ATX case.
When it comes to getting retro hardware running again, there are many approaches. On one hand, the easiest path could be to emulate the hardware on something modern, using nothing but software to bring it back to life. On the other, many prefer to restore the original hardware itself and make sure everything is exactly as it was when it was new. A middle way exists, though, thanks to the widespread adoption of FPGAs which allow for programmable hardware emulation and [Jo] has come up with a new implementation of the Commodore 64 by taking this path.
The project is called the VIC64-T9K and is meant as a proof-of-concept that can run the Commodore 64’s VIC-II video chip alongside a 6502 CPU on the inexpensive Tang Nano 9k FPGA. Taking inspiration from the C64_MiSTer project, another FPGA implementation of the C64 based on the DE10-Nano FPGA, it doesn’t implement everything an original Commodore system would have had, but it does provide most of the core hardware needed to run a system. The project supports HDMI video with a custom kernel, and [Jo] has used it to get a few demos running including sprite animations.
Today we heard from [Richard James Howe] about his new CPU. This new 16-bit CPU is implemented in VHDL for an FPGA.
The really cool thing about this CPU is that it eschews the typical program counter (PC) and replaces it with a linear-feedback shift register (LFSR). Apparently an LFSR can be implemented in hardware with fewer transistors than are required by an adder.
Usually the program counter in your CPU increments by one, each time indicating the location of the next instruction to fetch and execute. When you replace your program counter with an LFSR it still does the same thing, indicating the next instruction to fetch and execute, but now those instructions are scattered pseudo-randomly throughout your address space!
If you’re into retro CPUs and don’t shy away from wiring old-school voltages, [Mark]’s latest Intel 8080 build will surely spark your enthusiasm. [Mark] has built a full system board for the venerable 8080A-1, pushing it to run at a slick 3.125 MHz. Remarkable is that he’s done so using a modern Microchip FPGA, without vendor lock-in or proprietary flashing tools. Every step is open source.
Getting this vintage setup to work required more than logical tinkering. Mark’s board supplies the ±5 V and +12 V rails the 8080 demands, plus clock and memory interfacing via the M2GL005-TQG144I FPGA. The design is lean: two-layer PCB, basic level-shifters, and a CM32 micro as USB-to-UART fallback. Not everything went smoothly: incorrect footprints, misrouted gate drivers, thermal runaway in the clock section; but he managed to tackle it.
What sets this project apart is the resurrection of a nearly 50-year-old CPU. It’s also, how thoroughly thought-out the modern bridge is—from bitstream loading via OpenOCD to clever debugging of crystal oscillator drift using a scope. [Mark]’s love of the architecture and attention to low-level detail makes this more than a show-off build. Continue reading “Vintage Intel 8080 Runs On A Modern FPGA”→
Our hacker [Andrew Zonenberg] reports in on his open-source high-speed Ethernet switch. He hasn’t finished yet, but progress has been made.
If you were wondering what might be involved in a high-speed Ethernet switch implementation look no further. He’s been working on this project, on and off, since 2012. His design now includes a dizzying array of parts. [Andrew] managed to snag some XCKU5P FPGAs for cheap, paying two cents in the dollar, and having access to this fairly high-powered hardware affected the project’s direction.
