fpga

535 Articles

David Williams Is “FPGA-Curious”

December 6, 2019 by 17 Comments

If you hadn’t noticed, we had a bit of an FPGA theme running at this year’s Superconference. Why? Because the open-source FPGA toolchain is ripening, and because many of the problems that hackers (and academics) are tackling these days have become complex enough to warrant using them. A case in point: David Williams is a university professor who just wanted to build a quadruped robotics project. Each leg has a complex set of motors, motor drivers, sensors, and other feedback mechanisms. Centralizing all of this data put real strains on the robot’s network, and with so many devices the microcontrollers were running out of GPIOs. This lead him to become, in his words, “FPGA-curious”.

If you’re looking for a gentle introduction to the state of the art in open-source FPGAs, this is your talk. David covers everything, from a bird’s eye view of hardware description languages, through the entire Yosys-based open-source toolchain, and even through to embedding soft-CPUs into the FPGA fabric. And that’s just the first 18 minutes. (Slides for your enjoyment, and you can watch the talk embedded below the break.)
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Gameslab: The Other FPGA Game Console Badge

December 6, 2019 by 2 Comments

Anyone who was at Supercon will no doubt remember the badges that dangled around everyone’s neck. Some were reasonable, while some were neck-straining monsters that added anything and everything to hack the badge into something cool. We saw everything from AI cameras to a fully autonomous vehicle being worn with pride.

Sadly, one that we missed was Gameslab, [Craig J. Bishop]’s FPGA-based portable game console. No, not that FPGA-based game console; in an example of great minds thinking alike, [Craig] had actually been toying with his own handheld console design for quite some time. And we have to say the results are stunning.

The FPGA at the heart of this is a Xilinx Zynq FPGA-ARM Cortex A9 combo SoC, normally a prohibitively expensive monster of a chip. When [Craig] found “refurbished” Zynq chips on eBay for less than 10% of the cost of new units, it was literally game-on for the build. The console required a six-layer PCB to support the big BGA chip and the hundreds of support components around it. There’s a 5″ TFT touchscreen with a video controller implemented in the FPGA, a stereo sound system, and all the buttons and thumbsticks you’d expect on a modern console.

For our money, the best part is the case, about which [Craig] has yet to share any details. But it looks like a machined aluminum plate with wide chamfers around each cutout that contrast nicely with the brushed surface. We’ll be looking forward to more details on that and on progress with Gameslab.

A Fantastic Frontier Of FPGA Flexibility Found In The 2019 Supercon Badge

November 29, 2019 by 7 Comments

We have just concluded a successful Hackaday Superconference where a highlight for many was digging into this year’s hardware badge. Shaped in the general form of a Game Boy handheld gaming console, the heart of the badge is a large FPGA opening up new and exciting potential for badge hacking.

Beyond our normal tools of compiling custom code or modifying hardware with a soldering iron, we now have the option to change core hardware behavior with Verilog. And people explored this new frontier to great effect, as seen at the badge hacking ceremony. (Video embedded below.)

FPGAs are not new, technically speaking, why are they exciting now? We can thank their recent growth in capability, their rapidly falling cost, and the relatively new availability of open source toolchains. These developments elevated FPGA into one of the most exciting trends in hardware today, so this year’s badge master [Sprite_TM] built an open FPGA playground for several hundred of his closest Supercon friends. Let’s take a look at what people were able to accomplish in just a few days using this unique and powerful hardware.

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Old Cisco WAN Card Turned FPGA Playground

November 20, 2019 by 33 Comments

Many of us think of FPGAs as some new cutting edge technology, but the fact of the matter is that they’ve been around for quite some time. They’ve just traditionally been used in hardware that’s too expensive for us lowly hackers. A case in point is the Cisco HWIC-3G-CDMA WAN card. A decade ago these would have been part of a router valued in the tens of thousands of dollars, but today they can be had for less than $10 USD on eBay. At that price, [Tom Verbeure] thought it would be worth finding out if they could be repurposed as generic FPGA experimentation devices.

So as not to keep you in suspense, the short answer is a resounding yes. In the end, all [Tom] had to do was figure out what voltages the HWIC-3G-CDMA was expecting on the edge connector, and solder a 2×5 connector onto the helpfully labeled JTAG header. Once powered up and connected to the computer, Intel’s Quartus Programmer software immediately picked up the board’s Cyclone II EP2C35F484C8 chip. The blinking LEDs seen in the video after the break serve as proof that these bargain bin gadgets are ripe for hacking.

Unfortunately, there’s a catch. After studying the rest of the components on the board, [Tom] eventually came to the conclusion that the HWIC-3G-CDMA has no means of actually storing the FPGA’s bitstream. Presumably it was provided by the router itself during startup. If you just want to keep the board tethered to your computer for experimenting, that’s not really a big deal. But if you want to use it in some kind of project, you’ll need to include a microcontroller capable of pushing the roughly 1 MB bitstream into the FPGA to kick things off.

It might not be as easy to get up and running as the 2019 Hackaday Superconference badge, but it’s certainly a lot easier to get your hands on.

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A Scratch-built RISC-V CPU In An FPGA

November 19, 2019 by 17 Comments

“RISC architecture is going to change everything”, which is why [SHAOS] is building this cool RISC-V DIY retro-style computer.

The project took inspiration from another hacker’s work in building a RISC-V emulator; shared in the Hackaday FPGA chat. He took it a bit further and got it going on an UPDuino v2.0 board which features a iCE40 FPGA from Lattice.

The board passes all the tests for the RISC-V subset he’s aiming for and even run some Zephry RTOS examples. He’s done a really good job of documenting how he got the code to run as well as many of the experiments he’s run so far. All the project files for ICEcube2 software are posted. It’s not the only RISC-V CPU we’ve seen in an FPGA, but the code is actually very clear and worth a read if you’re into such things.

We think anyone interested in duplicating his work could do so somewhat easily and start playing around with this increasingly popular architecture. Or at least get some LED’s blinking in an arcane but meaningful way. Video after the break.

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Behind The Scenes Of The 2019 Superconference Badge

November 16, 2019 by 7 Comments

If you count yourself among the several hundred of our closest friends that have joined us at Supplyframe HQ for the 2019 Hackaday Superconference, then by now you’ll have your hands on one of this year’s incredible FPGA badges. It should come as no surprise that an incredible amount of time and effort went into developing and manufacturing this exceptionally unique piece of hardware; the slick gadget in your hands today took nearly an entire year to develop, and work continued on it until very literally the last possible moment.

Badge designer Jeroen Domburg (aka Sprite_TM), Hackaday staff, and a team of dedicated volunteers were still putting the final touches on these ambitious devices less than 24 hours before they were distributed to the first wave of Superconference attendees. Naturally, that’s not exactly how things were supposed to go. But when you’ve got a group of people that want to push the envelope and build something truly incredible, convincing them to actually stop working can be a challenge in itself.

In fact, development of the badge is still ongoing. Fixes and improvements are being made to the software even as you read this, and if you haven’t already, you should upgrade your badge to make sure you’ve got the latest and greatest from our international team of wizards. We all know that conference badges have an unfortunate habit of languishing on the shelf and collecting dust, but the 2019 Superconference badge was built to challenge you for longer than just one weekend. Consider yourself warned: for every Supercon badge that gets tossed in a drawer come Monday, Sprite_TM will shed a single tear.

After the break, come along as we turn back the clock and take a look at the last minute dash to get 500+ badges programmed and ready to go before the doors opened for the 2019 Hackaday Superconference.

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Speeding Up IOTA Proof Of Work Using FPGAs

November 16, 2019 by 5 Comments

Blockchain has existed as a concept since the early 1990s, but keeping a distributed ledger for IoT transactions wasn’t widely implemented until IOTA developed Tangle. The blockchain company was initially founded as a hardware startup and pivoted to work on transactional settlement for IoT. The Tangle, their distributed ledger architecture based on a directed acyclic graph (DAG) works as a “blockchain without the blocks and the chain”.

As its name implies, the Tangle is a web of transactions that references its past two transactions and a subsection of other transactions. Rather than miners and stakers being responsible for overall consensus, all active participants are involved in the approval of transactions. The transaction process requires the client to sign with their private keys, select two random unconfirmed transactions to be referenced, and perform proof-of-work.

The proof-of-work has an unfortunately high difficulty as you might expect. The process is similar to finding a nonce in Bitcoin mining, although the difficulty is set at a lower threshold due to the transactions running on lower-power nodes. Even so, since IOTA transactions commonly occur on small embedded platforms this can take several minutes to complete, a relatively long time considering these are mere transactions.

Since Curl-P81 hashes should be computed in parallel, they can’t be computed efficiently on general purpose CPUs. The PiDiver 1.3, [Thomas Pototschnig]’s port of the IOTA Reference Implementation (IRI) PearlDiver, performs searches for nonces. Because it runs on FPGAs, it is able to speed up the proof-of-work by a factor of more than 140 when compared to a Raspberry Pi. The FPGA is able to calculate one round of the hash in a single clock cycle, and a complete hash in 85 cycles (as well as testing for a valid nonce). Seven parallel hashes can be calculated at once, giving 15.8MHash/s at a frequency of 188MHz. The proof-of-work takes ~300ms on the FPGA when compared to 90s on a Raspberry Pi, so this is a significant improvement in speed.

Since the project is open source, the core can be used by IRI for creating a modified version of their PearlDiver.  The board can be used as a Raspberry Pi HAT, although it can also be connected via USB to work without the Pi.

While this doesn’t address the security concerns of using IOTA with personal IoT devices, it is certainly a significant improvement on the speed of their proof-of-work process, and the software speedup is incredibly satisfying to watch.

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