fpga

535 Articles

E-ink Display Driven DIY

April 20, 2017 by 44 Comments

E-ink displays are awesome. Humans spent centuries reading non-backlit devices, and frankly it’s a lot easier on the eyes. But have you looked into driving one of these critters yourself? It’s a nightmare. So chapeau! to [Julien] for his FPGA-based implementation that not only uses our favorite open-source FPGA toolchain, and serves as an open reference implementation for anyone else who’s interested.

Getting just black and white on an E-ink display is relatively easy — just hit the ink pixels with the same signal over and over until they give up. Greyscale is made by applying much more nuanced voltages because the pixels are somewhat state-dependent. If the desired endpoint is a 50% grey, for instance, you’d hit it with a different pulse train if the pixel were now white versus if it were now black. (Ever notice that your e-book screen periodically does a white-black flash? It’s resetting all the pixels to a known state.) And that’s not even taking into account the hassles with the various crazy voltages that E-ink displays require, which [Julien] wisely handed off to a dedicated chip.

In the end, the device has to make 20-50 passes through the screen for one user-visible refresh. [Julien] found that the usual microcontrollers just weren’t capable of the speed that he wanted, hence the FPGA and custom waveform tables. We’ve seen E-ink hacks before, and [Julien] is standing on the shoulders of giants, most notably those of [Petteri Aimonen] and [Sprite_tm]. [Julien]’s hack has the fastest updates we’ve ever seen.

We still can’t wait for the day that there is a general-purpose E-ink driver chip out there for pennies, because nearly every project we make with a backlit display would look better, and chew through the batteries slower, with E-ink. In the meantime, [Julien]’s FPGA implementation is pretty close, and it’s fully open.

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Lattice ICE40 FPGA Configured By Linux Kernel

April 13, 2017 by 15 Comments

The Linux kernel recently added support for loading firmware into an FPGA via the FPGA Manager Framework. [OpenTechLab] has built a driver for the Lattice iCE40 FPGA (same chip used on the iCEStick and other development boards). One attraction to the iCE40 is there is an open source toolchain called iCEStorm.

Even if you aren’t specifically interested in FPGAs, the discussion about Linux device drivers is good background. The principles would apply to other drivers, and would definitely apply if you want to write another FPGA loader.

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Veni, Vidi, ViciLogic Teaches You Digital Logic Interactively

March 31, 2017 by 6 Comments

This is about the time of the year you realize you aren’t going to keep all of those new year’s resolutions you made. However, if one of them was to learn VHDL and FPGAs, you might be in luck. Vicilogic has a free course in Fundamentals of Digital Systems. You do have to register, but it didn’t even verify our e-mail address, so it shouldn’t be too onerous to sign up.

Associated with the National University of Ireland Galway, the training is high quality and offers animated demos in your browser of the digital circuitry. You can even control the demos yourself. You’d think the work was occurring in some browser script, but according to the site, the demos are tied to real FPGA boards. You can supposedly look in on them as you use them with a video stream, but we never saw that working so your mileage may vary. If you want a preview of what it looks like, check out the video below. There’s guided exercises and also quizzes where you have to interact with the demos.

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Printer Scrap Becomes FPGA Devboard

February 27, 2017 by 7 Comments

These days, if you want to start learning about FPGAs, it can be a daunting experience. There’s a huge variety of different platforms and devboards and it can be difficult to know where to start. [RoGeorge] decided to take a different tack. Like a 16-year-old drag racer, he decided to run what he brung – a printer control panel cum FPGA development board (Romanian, get your Google Translate on).

[RoGeorge] was lucky enough to score a couple of seemingly defective control panels from HP Laserjets discarded by his workplace. Seeing potentially good parts going to waste, like keypads and LCDs, he decided to investigate them further – finding a 50,000 gate Xilinx Spartan IIE running the show. Never one to say no to opportunity, [RoGeorge] dived in to learning how to work with FPGAs.

The forum posts are a great crash course in working with this sort of embedded FPGA platform. [RoGeorge] covers initial mapping of the peripherals on the board & finding a JTAG connector and programming solution, before moving on to basic FPGA programming and even covers the differences between sequential programming on microcontrollers and the parallel operation of FPGAs. Even if you don’t intend to get down and dirty with the technology, spend half an hour reading these posts and you’ll be far more knowledgeable about how they work!

In the end, [RoGeorge] showed how to teach yourself to work with FPGAs for the price of a couple of programming cables – not a mean feat by any means. It’s a testament to the hacker spirit, and reminds us of [SpriteTM]’s efforts in hacking hard drive controllers.

Zork Comes To Custom FPGA CPU (Again)

February 21, 2017 by 9 Comments

[Robert Baruch] wanted to tackle a CPU project using an FPGA. One problem you always have is you can either mimic something that has tools and applications or  you can go your own way and just build everything from scratch (which is much harder).

[Robert] took the mimic approach–sort of. He built a CPU with the express idea of running Infocom’s Z-machine virtual machine, which allows it to play Zork. So at least when you are done, you don’t have to explain to your non-tech friends that it only blinks an LED. Check out the video, below, for more details.

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Adding IceZero To The Raspberry Pi

February 8, 2017 by 24 Comments

[Kevinhub] noticed there were quite a few FPGA hats for the Raspberry Pi. Instead going out and buying one of these boards like a filthy commoner, he decided to spin up his own FPGA Pi accessory. This IceZero FPGA board combines the best features from other FPiGA boards, and does it in a form factor that fits right on top of the minuscule Pi Zero.

If you think slapping a Lattice FPGA onto a Pi has been done before, you’re right. Here’s a hat for the Pi using an iCE5LP4K-SG48, an FPGA with 3520 LUTs. The CAT Board from Xess has a slightly bigger FPGA with 7680 logic cells, and the FleaOhm has a monster FPGA on board that costs about $70 USD.

[Kevin]’s IceZero is at the lower end of these Raspberry Pi FPGA hats, using a Lattice ICE40HX4K. That’s only 3520 logic cells, but it only costs about $7 USD in quantity one. The board design is a standard two layer board that shouldn’t be too terrible for hand soldering. The boards are shared on OSH Park, should you want to test this little guy out.

This Pi Hat is specifically designed to be used with Project IceStorm, the Open toolchain for Lattice’s iCE40 FPGAs. That means there’s already a few projects out in the wild that can be easily ported to this platform, and already [Kevin] has a logic SUMP example going on his board.

Ice, Ice, Radio Uses FPGA

January 23, 2017 by 24 Comments

Building a software defined radio (SDR) involves many trades offs. But one of the most fundamental is should you use an FPGA or a CPU to do the processing. Of course, if you are piping data to a PC, the answer is probably a CPU. But if you are doing the whole system, it is a vexing choice. The FPGA can handle lots of data all at one time but is somewhat more difficult to develop and modify. CPUs using software are flexible–especially for coding user interfaces, networking connections, and the like) but don’t always have enough horsepower to cope with signal processing tasks (and, yes, it depends on the CPU).

[Eric Brombaugh] sidestepped that trade off. He used a board with both an ARM processor and an ICE FPGA at the heart of his SDR design. He uses three custom boards: one is the CPU/FPGA board, another is a 10-bit converter that can sample at 40 MSPS (sufficient to decode to 20 MHz), and an I2S DAC to produce audio. Each board has its own page linked from the main project.

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