Zynq And The OPL3 Music Synthesizer

August 10, 2015 by Al Williams 21 Comments

We’re big fans of the Zynq, which is an answer to the question: what do you get when you cross a big ARM processor with a big FPGA? So it isn’t surprising that [GregTaylor’s] project to emulate the OPL3 FM Synthesis chip in an FPGA using the Zynq caught our eye.

The OPL3 (also known as the Yamaha YMF262) was a very common MIDI chip on older PC sound cards. If you had a Sound Blaster Pro or 16 board, you had an OPL3 chip in your PC. The OPL3 was responsible for a lot of the music you associate with vintage video games like Doom. [Greg] not only duplicated the chip’s functions, but also ported imfplay from DOS to run on the Zynq’s ARM processors so he could reproduce those old video game sounds.

The Zybo board that [Greg] uses includes an Analog Devices SSM2603 audio codec with dual 24-bit DACs and 256X oversampling. However, the interface to the codec is isolated in the code, so it ought to be possible to port the design to other hardware without much trouble.

To better match the original device’s sampling rate with the faster CODEC, this design runs at a slightly slower frequency than the OPL3, but thanks to the efficient FPGA logic, the new device can easily keep up with the 49.7 kHz sample rate.

Using an FPGA to emulate an OPL3 might seem to be overkill, but we’ve seen worse. If you prefer to do your synthesis old school, you can probably get a bulk price on 555 chips.

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Hacking A Universal Assembler

August 6, 2015 by Al Williams 30 Comments

I have always laughed at people who keep multitools–those modern Swiss army knives–in their toolbox. To me, the whole premise of a multitool is that they keep me from going to the toolbox. If I’ve got time to go to the garage, I’m going to get the right tool for the job.

Not that I don’t like a good multitool. They are expedient and great to get a job done. That’s kind of the way I feel about axasm — a universal assembler I’ve been hacking together. To call it a cross assembler hack doesn’t do it justice. It is a huge and ugly hack, but it does get the job done. If I needed something serious, I’d go to the tool box and get a real assembler, but sometimes you just want to use what’s in your pocket.

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Teach Yourself Verilog With This Tiny CPU Design

August 1, 2015 by Al Williams 5 Comments

You probably couldn’t write a decent novel if you’d never read a novel. Learning to do something often involves studying what other people did before you. One problem with trying to learn new technology is finding something simple enough to start your studies.

[InfiniteNOP] wanted to get his feet wet writing CPUs and developed a simple 8-bit architecture that would be a good start for a classroom or self-study. It is a work in progress, so there may be a few bugs in it still to squash, but squashing bugs might be educational too. You can read the documentation in the HACKING file for details on the architecture. Briefly, the instruction’s top four bits encode the operation, while the last four bits select the register operands (there are four registers).

[InfiniteNOP] used the Xilinx tools to simulate and synthesize the CPU, but we thought it might be a good excuse to play with EDAPlayground. You can find a testbench that works with EDAPlayground, although you’ll probably want to update the CPU files to match the latest version.

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Open Source FPGA Toolchain Builds CPU

July 28, 2015 by Al Williams 24 Comments

When you develop software, you need some kind of toolchain. For example, to develop for an ARM processor, you need a suitable C compiler, a linker, a library, and a programmer. FPGAs use a similar set of tools. However, instead of converting source code to machine language, these tools map the intent of your source code into configuration of FPGA elements and the connections between them.

There’s some variation, but the basic flow in an FPGA build is to use a synthesizer to convert Verilog or VHDL to a physical design. Then a mapper maps that design to the physical elements available on a particular FPGA. Finally, a place and route step determines how to put those elements in a way that they can be interconnected. The final step is to generate a bitstream the chip understands and somehow loading it to the chip (usually via JTAG or by programming a chip or an external EEPROM).

One problem with making your own tools is that the manufacturers typically hold the bitstream format and other essential details close to their chest. Of course, anything can be reverse engineered (with difficulty) and [James Bowman] was able to build a minimal CPU using an open source Lattice toolchain. The project relies on several open source projects, including IceStorm, which provides configuration tools for Lattice iCE40 FPGAs (there is a very inexpensive development platform available for this device).

We’ve covered IceStorm before. The IceStorm project provides three tools: one to produce the chip’s binary format from an ASCII representation (and the reverse conversion), a programmer for the iCEstick and HX8K development boards, and database that tells other open source tools about the device.

Those tools blend with other open source tools to form a complete toolchain–a great example of open source collaboration. Yosys does the synthesis (one of the tools available on the EDAPlayground site). The place and route is done by Arachne. The combined tools are now sufficient to build the J1A CPU and can even run a simple version of Forth. If you’ve ever wanted to play with an FPGA-based CPU design, you now have a $22 hardware option and free tools.

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Hackaday Prize Entry: An FPGA’d Propeller

July 21, 2015 by Brian Benchoff 23 Comments

The Parallax Propeller is an exceptionally interesting chip that doesn’t get the love it deserves. It’s a 32-bit microcontroller with eight independent cores that are each powerful enough to do some real computation. Around this time last year, the source for the Propeller was opened up and released under GPL 3.0, along with the mask ROM and an interpreter for the Propeller-specific language, Spin. This release is not only a great educational opportunity, but a marvelous occasion to build some really cool hardware as [antti.lukats] is doing with the Soft Propeller.

[antti]’s Soft Propeller is based on the Xilinx ZYNQ-7000, a System on Chip that combines a dual core ARM Cortex A9 with an FPGA with enough logic gates to become a Propeller. The board also has 16MB of Flash used for configuration and everything fits on a Propeller-compatible DIP 40 pinout. If you’ve ever wanted to play around with FPGAs and high-power ARM devices, this is the project for you.

[antti] already has the Propeller Verilog running on his board, and with just a bit more than 50% of the LUTs used, it might even be possible to fit the upcoming Propeller 2 on this chip. This build is just one small part of a much larger and more ambitious project: [antti] is working on a similar device with HDMI, USB, a MicroSD, and 32MB of DDR2 RAM. This will also be stuffed into a DIP40 format, making it an incredibly powerful system that’s just a bit larger than a stick of gum.

The 2015 Hackaday Prize is sponsored by:

Learn FPGAs In Your Browser

July 21, 2015 by Al Williams 40 Comments

FPGAs aren’t really programmed, they are configured. Most designers use Verilog or VHDL to describe the desired circuit configuration. Developers typically simulate these configurations before committing them to silicon (a good habit, especially if you ever graduate from FPGAs to ASICs where changes are very expensive). That simulation takes a lot of software you have to install and learn, right?

Not necessarily. You can do e-mail, word processing, and PCB layout in your browser. Why not FPGA design? The EDAPlayground website provides two editor views: one for your main “code” and another for the testbench (the simulation driver you use to test your design). You can even open multiple files, if you have a complex design.

Once you’ve entered your Verilog or VHDL (or picked one of many examples) you can run the simulation and see the result right in your browser. No software to install, and–outside of actually learning VHDL or Verilog–not much learning curve.

As [Strauburn], [combinatorylogic], and others commented on our recent post about a VHDL CPU, you can do a lot of learning without ever having your hands on real hardware. The web site gives you access to several different tools (useful if you want to see how your code will behave on different tools) and also many standard verification libraries. There are limited synthesis tools, but honestly, if you want to go to real hardware, you are going to want the vendor tools for the specific FPGA you are using.

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Designing A CPU In VHDL For FPGAs: OMG.

July 20, 2015 by Elliot Williams 68 Comments

If you’ve been thinking about playing around with FPGAs and/or are interested in CPU design, [Domipheus] has started a blog post series that you should check out. Normally we’d wait until the whole series is done to post about it, but it’s looking so good, that we thought we’d share it with you while it’s still in progress. So far, there are five parts.

In Part One, [Domipheus] goes through his rationale and plans for the CPU. If you’re at all interested in following along, this post is a must-read. The summary, though, is that he’s aiming to make a stripped-down 16-bit processor on a Spartan 6+ FPGA with basic arithmetic and control flow, and write an assembler for it.

In Part Two, [Domipheus] goes over the nitty-gritty of getting VHDL code rendered and uploaded to the FPGA, and as an example builds up the CPU’s eight registers. If you’re new to FPGAs, pay special attention to the test bench code at the end of the post. Xilinx’s ISE package makes building a test suite for your FPGA code pretty easy, and given the eventual complexity of the system, it’s a great idea to have tests set up for each stage. Testing will be a recurring theme throughout the rest of the posts.

In Part Three, [Domipheus] works through his choices for the instruction set and starts writes up the instruction set decoder. In Part Four, we get to see an ALU and the jump commands are implemented. Part Five builds up a bare-bones control unit and connects the decoder, ALU, and registers together to do some math and count up.

We can’t wait for further installments. If you’re interested in this sort of thing, and are following [Domipheus]’s progress, be sure to let him know: we gotta keep him working.

Of course, this isn’t the first time anyone’s built a soft-CPU in an FPGA. (The OMG was added mostly to go along with the other TLAs.) Here’s a tiny one, a big one, and a bizarre one.