RISC-V

105 Articles

What Can You Run On A 1960s Univac? Anything You’re Willing To Wait For!

April 18, 2026 by 14 Comments

There are two UNIVAC 1219B computers that have survived since the 1960s and one of them is even operational. [Nathan Farlow] wanted to run a Minecraft server on it, so he did. After a lot of work, of course, which is described in a detailed blog post, and, a YouTube video by [TheScienceElf] we’ve embedded below.

The UNIVAC is a seriously weird architecture by modern standards: it’s got eighteen-bit words — yeah, not even a power of two — and one’s compliment arithmatic with a weird signed zero thing going on. There’s one 36-bit and one 18-bit register, and only 40,960 words of memory. Eighteen-bit words. Yeah, it was the 1960s and they were making it up as they went along.

[Nathan] wasn’t, entirely, as this weird system is both well-documented and already had an emulator — in BASIC, of all things. [TheScienceElf] used the docs and the existing emulator to recreate his own in Rust so he could test their somewhat crazy plan without wasting cycles on real hardware. The plan? Well, there are really only two options if you want to build modern software for a niche architecture: one is to add niche support to something like GCC, and the other is to write a RISC V emulator and compile to that. We’ve seen that second one before, and that’s the route [Nathan] took.

Of course, [Nathan] is a machine learning guy, so he made the best possible use of LLMs — though it’s interesting to see that unlike Z80 Assembly, Claude Code really couldn’t wrap its virtual head around the UNIVAC’s assembly language, and [Nathan] had to bang out the RISC V emulator himself. Emulator in hand, [Nathan] and friends had code to run on the museum UNIVAC. A single frame of an NES game took 40 minutes, but hey, at least it finished before they got back from lunch.

[TheScienceElf]’s YouTube treatment teases hosting Minecraft, but it wasn’t a full server, just the login portion. That they were able to get TCP/IP over serial and set up a handshake between a 2020s laptop and a 1960s computer is still mighty impressive. Just the work the Vintage Computer Federation put in to get and keep this antique running is mighty impressive all on its own, but it’s wonderful they let people play with it.

Continue reading “What Can You Run On A 1960s Univac? Anything You’re Willing To Wait For!” →

Espressif’s New ESP32-S31: Dual-Core RISC-V With WiFi 6 And GBit Ethernet

April 8, 2026 by 41 Comments

In a move that’s no doubt going to upset and confuse many, Espressif has released its newest microcontroller — the ESP32-S31. The confusing part here is that the ESP32-S series was always the one based on Tensilica Xtensa LX7 cores, while the ESP32-C series was the one using RISC-V cores.

That said, if one looks at it as a beefier -S3 MCU it does have some appealing upgrades. The most obvious improvements are with the use of WiFi 6, as well as Bluetooth Classic and LE 5.4, including LE Audio. There is also Thread and Zigbee support for those who are into such things.

The Ethernet MAC got a bump from the 100 Mbit RMII MAC in previous MCUs and is now gigabit-rated, while the number of GPIO is significantly higher at 60 instead of 45 on the -S3. On the RAM side, things are mostly the same, except for DDR PSRAM support, with octal SPI offering up to 250 MHz compared to 80 MHz on the -S3.

On the CPU side the up-to-320 MHz RISC-V cores are likely to be about as powerful as the 240 MHz LX7 cores in the -S3, based on the ESP32-C series performance in terms of IPC. Overall it does seem like a pretty nice MCU, it’s just confusing that it doesn’t use LX7 cores with the series it was put into. When this MCU will be available for sale doesn’t seem to be known yet, with only samples available to select customers.

Arduino Code? On My 8051? It’s More Likely Than You Think

March 22, 2026 by 29 Comments

The 8051 was an 8-bit Harvard-architecture microcontroller first put out by Intel in 1980.  They’ve since discontinued that line, but it lives on in the low-cost STC8 family of chips, which is especially popular in Asia. They’re cheap as, well, chips — under 1$ — but lack compatibility with modern toolchains. If you’re happy with C, then you’re fine, but if you want to plus-plus it up and use all those handy-dandy shortcuts provided by the Arduino ecosystem, you’re out of luck. Or rather, you were, until [Bùi Trịnh Thế Viên] aka [thevien257] came up with a workaround.

The workaround is delightfully Hack-y. One could, conceivably, port a compiler for Arduino’s  Wiring to the 8051, but that’s not what [Viên] did, probably because that would be a lot of work. There isn’t even a truly modern toolchain to put plain C on this chip. Instead, [Viên] started with rv51, a RISC-V emulator written in 8051 assembly language by [cryozap]. RISC-V is a lot easier to work with and, frankly, a more useful skill to build up.

Continue reading “Arduino Code? On My 8051? It’s More Likely Than You Think” →

WCH CH32M030: Another Microcontroller To Watch Out For

January 16, 2026 by 49 Comments

One of the joys of writing for Hackaday comes in following the world of new semiconductor devices, spotting interesting ones while they are still just entries on manufacturer websites, and then waiting for commonly-available dev boards. With Chinese parts there’s always a period in which Chinese manufacturers and nobody else has them, and then they quietly appear on AliExpress.

All of which brings us to the WCH CH32M030, a chip that’s been on the radar for a while and has finally broken cover. It’s the CH32 RISC-V microcontroller you may be familiar with, but with a set of four half-bridge drivers on board for running motors. A handy, cheap, and very smart motor controller, if you will.

There’s been at  least one Chinese CH32M030 dev board (Chinese language) online for a while now, but the one listed on AliExpress appears to be a different design. At the time of writing the most popular one is still showing fewer than 20 sales, so we’re getting in at the ground floor here.

We think this chip is of interest because it has the potential to be used in low price robotic projects, replacing as it does a couple of parts or modules in one go. If you use it, we’d like to hear from you!

World’s Cheapest ARM Debugger Is Actually RISC-V

October 22, 2025 by 18 Comments

[bogdanthegeek] has a lot of experience with the ARM platform, and their latest escapade into working with cheap ARM chips recovered from disposable vapes involved a realization that it was just plain wrong to debug such recovered silicon with something as expensive as a Pi Pico. No, they needed to build a debugger using the super cheap CH32V003.

What follows is an interesting tour around ARM Debug Access Port (DAP) programmers and creating a practical USB-connected device that actually works with modern toolchains. The first problem to be solved was that of host connectivity. These days, it’s USB or go home, which immediately limits the microcontrollers you can choose. Luckily for [Bogdan], they were aware of the excellent work by [cnlohr] on wedging low-speed USB support onto the RISC-V CH32v003 with the software-only bit-banging rv003usb, which provided a starting point. The next issue was to check for interrupt-driven endpoint support (needed for low-speed USB) in the Mac OS X kernel, which they knew was being dropped at an alarming rate (well, at least for full-speed). Luckily, the CMSIS-DAP standard required support for interrupt-driven USB endpoints, so kernel support was likely intact.

Next, [Bogdan] noticed that the DAPLink project had been ported to the bigger, native-USB WCH chips like the CH32V203, so it was a matter of porting this code to the diminutive CH32V003 using the rv003usb stack for the USB support using [cnlohr]’s ch32fun toolchain. There were a few bumps along the way with a lack of clarity in the DAPLink code, and some inconsistencies (across platforms) with the USB library dependencies of the upstream tool pyOCD, but they did get some tools working on at least Mac OS and some others on Linux. Which was nice.

We’ve covered the CH32V003 a fair bit, with people trying to give it all kinds of big-CPU tricks, such as speech recognition (of sorts) or even building a supercluster.

160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed

July 7, 2025 by 20 Comments

Aside from GPUs, you don’t hear much about co-processors these days. [bitluni] perhaps missed those days, because he found a way to squeeze a 160 core RISC V supercluster onto a single m.2 board, and shared it all on GitHub.

OK, sure, each core isn’t impressive– he’s using CH32V003, so each core is only running at 48 MHz, but with 160 of them, surely it can do something? This is a supercomputer by mid-80s standards, after all.  Well, like anyone else with massive parallelism, [bitluni] decided to try a raymarcher. It’s not going to replace RTX anytime soon, but it makes for a good demo.

Like his previous m.2 project, an LED matrix,  the cluster is communicating over PCIe via a WCH CH382 serial interface. Unlike that project, blinkenlights weren’t possible: the tiny, hair-thin traces couldn’t carry enough power to run the cores and indicator LEDs at once. With the power issue sorted, the serial interface is the big bottleneck. It turns out this cluster can crunch numbers much faster than it can communicate. That might be a software issue, however, as the cluster isn’t using all of the CH382’s bandwidth at the moment. While that gets sorted there are low-bandwidth, compute-heavy tasks he can set for the cluster. [bitluni] won’t have trouble thinking of them; he has a certain amount of experience with RISCV microcontroller clusters.

We were tipped off to this video by [Steven Walters], who is truly a prince among men. If you are equally valorous, please consider dropping informational alms into our ever-present tip line. 

Continue reading “160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed” →

A RISC-V Operating System Instruction Manual

May 26, 2025 by 1 Comment

To some, an operating system is a burden or waste of resources, like those working on embedded systems and other low-power applications. To others it’s necessary, abstracting away hardware so that higher-level programming can be done. For most people it’s perhaps not thought of at all. But for a few, the operating system is the most interesting piece of software running on a computer and if you’d like to investigate what makes this often overlooked aspect of computer science interesting, take a look at this course on operating systems from Cornell University.

The operating system itself is called Earth and Grass Operating System because it splits the functionality of the operating system into three separate parts. The Earth layer involves dealing with hardware, the Grass layer involves hardware-independent aspects, and a third application layer implements other key operating system features. It’s built for a RISC-V processor, since that instruction set is completely open source and transparent about what it’s doing. It’s also incredibly small, coming in at around 2000 lines of code. The course covers nine areas, with the first six being core operating system functions and the remaining three covering more advanced operating system concepts.

For understanding the intricacies and sometimes mysterious ways that operating systems work, a course like this can go a long way into unraveling those mysteries and developing a deeper understanding of how it brings the hardware to work for higher-level software. We actually featured this operating system two years ago, before this course was created, which covers this project for those who like to take a more self-directed approach, or simply want a lightweight OS for a RISC-V system.