Sprite Graphics Accelerator on an FPGA

A demo running on a FPGA sprite accelerator

Graphics accelerators move operations to hardware, where they can be executed much faster. This is what allows your Raspberry Pi to display high definition video decently. [Andy]’s latest build is a 2D sprite engine, featuring hardware accelerated graphics on an FPGA.

In the simplest mode, the sprite engine just passes commands through to the LCD. This allows for basic control. The fun part sprite mode, which allows for sprites to be loaded onto the FPGA. At that point, you can show, hide, and move the sprite. By overlapping many sprites, you something like the demo shown above.

The FPGA is from Xilinx, and uses their Block RAM IP to store the state of the sprites. The actual sprite data is contained on a 128 Mb external flash chip, since they require significant space.

The game logic runs on a STM32 Cortex M4 microcontroller which communicates with the FPGA and orders the sprites around. The FPGA then deals with generating frames and sending them to the LCD screen, freeing up the microcontroller.

If you’re wondering about the LCD itself, it’s 3.2″, 640 x 360, and taken from a Ericsson U5 Vivaz cellphone. [Andy] has a detailed writeup on reverse engineering it. After the break, he gives us a video overview of the whole system.

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Counting Really, Really Fast With An FPGA

fast

During one of [Michael]’s many forum lurking sessions, he came across a discussion about frequency counting on a CPLD. He wondered if he could do the same on an FPGA, and how hard it would be to count high clock rates. As it turns out, it’s pretty hard with a naive solution. Being a bit more clever turns the task into a cakewalk, with a low-end FPGA being able to count clocks over 500 MHz.

The simplest solution for counting a clock would be to count a clock for a second with a huge, 30-bit counter. This is a terrible idea: long counters have a lot of propagation delays. Also, any sampling would have to run at least twice as fast as the input signal – not a great idea if you’re counting really fast clocks.

The solution is to have the input signal drive a very small counter – only five bits – and sample the counter using a slower clock on board the FPGA. [Michael] used a 5-bit Gray code, getting rid of the problem of the ‘11111’ to ‘00000’ rollover of a normal binary counter.

Because [Michael] is using a 5 bit clock with 31 edges sampled at 32 MHz, he can theoretically sample a 992 MHz clock. There isn’t a chance in hell of the Spartan 6 on his Papilio Pro board ever being able to measure that, but he is able to measure a 500 MHz clock, something that would be impossible without his clever bit of code.

An Online Course For FPGA And CPLD Development

FPGA

Over on the University of Reddit there’s a course for learning all about FPGAs and CPLDs. It’s just an introduction to digital logic, but with a teacher capable of building a CPLD motor control board and a video card out of logic chips, you’re bound to learn something.

The development board being used for this online course is an Altera EMP3032 CPLD conveniently included in the Introduction to FPGA and CPLD kit used in this course. It’s not a powerful device by any measure; it only has 32 macrocells and about 600 usable gates. You won’t be designing CPUs with this thing, but you will be able to grasp the concept of designing logic with code.

Future lessons include building binary counters, PWM-controlled LEDs, and a handheld LED POV device. In any event, it’s a great way to learn about how programmable logic actually works, and a fairly cheap way to get into the world of FPGAs and CPLDs. Introductory video below.

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Papilio Duo: FPGA, Logic Analyzer, Debugger, and Arduino Compatible

Back

It’s been a while since we’ve seen some new boards that combine an FPGA and an Arduino, so naturally the state of the art is a little bit behind. The latest from [Jack Gassett], the Papilio Duo, aims to change that by addressing all the complaints of the original Papilio and adding some neat, modern features that you would expect on a board designed in 2014.

On board the Duo is an ATMega32u4, the same chip used in the Arduino Leonardo, allowing for easy integration with your standard Arduino projects. The top of the board is where the real money is. There’s a Spartan 6 FPGA with 9k logic cells, enough to run emulate some of the classic computers of yore, including the famous SID chip, Yamaha YM2149, and the Atari POKEY (!).  With host and device USB, 512k or 2M of SRAM, and an ADC on the FPGA inputs, this board should be able to handle just about everything you would want to throw at it. There’s even a breakout for HDMI on the bottom.

There are a few interesting software features of the Duo, including a full debugger for the ATMega chip, thanks to an emulated Atmel JTAG ICE MKII. Yes, an Arduino-compatible board finally has a real debugger. The FPGA can also implement a 32 channel logic analyzer, making this not only an extremely powerful dev board, but also a useful tool to keep around the workbench.

Augmented Reality with an FPGA

 

bruceinabox

 

[Julie Wang] has created an augmented reality system on a Field Programmable Gate Array (FPGA). Augmented reality is nothing new – heck, these days even your tablet can do it. [Julie] has taken a slightly different approach though. She’s not using a processor at all. Her entire system, from capture, to image processing, to VGA signal output, is all instantiated in a FPGA.

Using the system is as simple as holding up a green square of cardboard. Viewing the world through an old camcorder, [Julie’s] project detects and tracks the green square. It then adds a 3D image of Cornell’s McGraw Tower on top of the green. The tower moves with the cardboard, appearing to be there. [Julie] injected a bit of humor into the project through the option of substituting the tower for an image of her professor, [Bruce Land].

[Julie] started with an NTSC video signal. The video is captured by a DE2-115 board with an Altera Cyclone IV FPGA. Once the signal was inside the FPGA, [Julie’s] code performs a median filter. A color detector finds an area of green pixels which are passed to a corner follower and corner median filter. The tower or Bruce images are loaded from ROM and overlaid on the video stream, which is then output via VGA.

The amazing part is that there is no microprocessor involved in any of the processing. Logic and state machines control the show. Great work [Julie], we hope [Bruce] gives you an A!

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Phenox: Wherein Quadcopters Get FPGAs

quad

The computing power inside a quadcopter is enough to read a few gyros and accelerometers, do some math, and figure out how much power to send to the motors. What if a quadcopter had immensely more computing power, and enough peripherals to do something cool? That’s what Phenox has done with a micro quad that is able to run Linux.

Phenox looks like any other micro quad, but under the hood things get a lot more interesting. Instead of the usual microcontroller-based control system, the Phenox features a ZINQ-7000 System on Chip, featuring an ARM core with an FPGA and a little bit of DDR3 memory. This allows the quad to run Linux, made even more interesting by the addition of two cameras (one forward facing, one down facing), a microphone, an IMU, and a range sensor. Basically, if you want a robotic pet that can hover, you wouldn’t do bad by starting with a Phenox.

The folks behind Phenox are putting up a Kickstarter tomorrow. No word on how much a base Phenox will run you, but it’ll probably be a little bit more than the cheap quads you can pick up from the usual Chinese retailers.

Videos below.

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A Z80 Retro Microcomputer for the Papilio Pro FPGA Board

z80

[Will] wrote a 128MHz Z80-based retro microcomputer which runs on a Papilio Pro board. For those who don’t know, the latter is built around a Spartan-6 LX9 FPGA so you may imagine that much work was required to implement all the computer features in VHDL. The T80 CPU core was taken from opencores, the SDRAM controller was imported from Mike Field’s work but [Will] implemented several additional functions on his own:

– a 4KB paged Memory Management Unit to translate the 16-bit (64KB) logical address space into a 26-bit (64MB) physical address space.

– a 16KB direct mapped cache to hide the SDRAM latency, using the FPGA internal block RAM

– a UART interface for external communications

He also ported CP/M-2.2, MP/M-II and UZI (a UNIX system) to the computer. His project is completely open-source and all the source code can be downloaded at the end of [Will]’s write up.

Thanks [hamster] for the tip.