IcePI Zero: A Pi Zero For FPGA

May 29, 2025 by 32 Comments

The Rasberry Pi Zero is a delightful form factor, with its GIPO and USB and HDMI, but it’s stuck using the same old ARM processor all the time. What if you wanted to change it up with some OpenSPARC, RISC V, OpenPOWER, or even your own oddball homebrew ISA and processor? Well, fret not, for [Chengyin Yao]’s IcePi Zero has got you covered with its ECP5 25F FPGA.

As the saying goes, you don’t tell an FPGA what to do, you tell it what to be. And with the ECP5 25F’s 24k LUTs, you can tell it to be quite a few different things. This means more work for the maker than plugging in a fixed processor, sure, but IcePi tries to make that as painless as possible with quality-of-life features like HDMI out (something missing from many FPGA dev boards), an onboard USB-to-JTAG converter (so you can just plug it in, no programmer needed), and even USB-C instead of the Pi’s old microUSB. There’s the expected SD card on one end, and 256 MiB of 166 MHz SDRAM on the other to make up for the FPGA’s paltry 112 KiB of onboard RAM.

Plus it’s a drop-in replacement for the Pi Zero, so if you’ve already got a project that’s got one of those running an emulator, you can fab one of these babies, spool up some Verilog, and enjoy running on bare metal. It seems like this device is just made for retro gaming handhelds, but we’d love to hear in the comments if you have other ideas what to do with this board– remember that an FPGA can be (almost) anything, even a GPU!

Currently, [Chengin Yao] is not selling the board, though they may reconsider due to demand in their Reddit thread. If you want one, you’ll have to call your favourite fabricator or etch your own PCB.

We’ve seen FPGAs before; most recently to create an absurdly fast 8080 processor. We’ve also seen DIY dev boards, like this one for the AMD Zyntac FPGA. Doing something fun with FPGAs? Drop us a tip! We’re happy [Chengin Yao] did, because this is amazing work, especially considering they are only 16 years old. We cannot wait to find out what they get up to next.

Two hands soldering components on a purpble PCB

Vintage Intel 8080 Runs On A Modern FPGA

May 26, 2025 by 5 Comments

If you’re into retro CPUs and don’t shy away from wiring old-school voltages, [Mark]’s latest Intel 8080 build will surely spark your enthusiasm. [Mark] has built a full system board for the venerable 8080A-1, pushing it to run at a slick 3.125 MHz. Remarkable is that he’s done so using a modern Microchip FPGA, without vendor lock-in or proprietary flashing tools. Every step is open source.

Getting this vintage setup to work required more than logical tinkering. Mark’s board supplies the ±5 V and +12 V rails the 8080 demands, plus clock and memory interfacing via the M2GL005-TQG144I FPGA. The design is lean: two-layer PCB, basic level-shifters, and a CM32 micro as USB-to-UART fallback. Not everything went smoothly: incorrect footprints, misrouted gate drivers, thermal runaway in the clock section; but he managed to tackle it.

What sets this project apart is the resurrection of a nearly 50-year-old CPU. It’s also, how thoroughly thought-out the modern bridge is—from bitstream loading via OpenOCD to clever debugging of crystal oscillator drift using a scope. [Mark]’s love of the architecture and attention to low-level detail makes this more than a show-off build.
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A SNES CPU Replacement Via FPGA

March 31, 2025 by 18 Comments

Let’s say you had a SNES with a busted CPU. What would you do? Your SNES would be through! That is, unless, you had a replacement based on an FPGA. [leonllr] has been developing just such a thing.

The project was spawned out of necessity. [leonllr] had purchased a SNES which was struck down with a dead CPU—in particular, a defective S-CPU revision A. A search for replacements only found expensive examples, and ones that were most likely stripped from working machines. A better solution was necessary.

Hence, a project to build a replacement version of the chip using the ICE40HX8K FPGA. Available for less than $20 USD, it’s affordable, available, and has enough logic cells to do the job. It’s not just a theoretical or paper build, either. [leonllr] has developed a practical installation method to hook the ICE40HX8K up to real hardware, which uses two flex PCBs to go from the FPGA mainboard to the SNES motherboard itself. As for the IP on the FPGA, the core of the CPU itself sprung from the SNESTANG project, which previously recreated the Super Nintendo on Sipeed Tang FPGA boards. As it stands, boards are routed, and production is the next step.

It’s nice to see classic hardware resurrected by any means necessary. Even if you can’t get a whole bare metal SNES, you might be able to use half of one with a little help from an FPGA. We’ve seen similar work on other platforms, too. Meanwhile, if you’re working to recreate Nintendo 64 graphics chips in your own basement, or something equally weird, don’t hesitate to let us know!

Reconfigurable FPGA For Single Photon Measurements

March 30, 2025 by 6 Comments

Detecting single photons can be seen as the backbone of cutting-edge applications like LiDAR, medical imaging, and secure optical communication. Miss one, and critical information could be lost forever. That’s where FPGA-based instrumentation comes in, delivering picosecond-level precision with zero dead time. If you are intrigued, consider sitting in on the 1-hour webinar that [Dr. Jason Ball], engineer at Liquid Instruments, will host on April 15th. You can read the announcement here.

Before you sign up and move on, we’ll peek into a bit of the matter upfront. The power lies in the hardware’s flexibility and speed. It has the ability to timestamp every photon event with a staggering 10 ps resolution. That’s comparable to measuring the time it takes light to travel just a few millimeters. Unlike traditional photon counters that choke on high event rates, this FPGA-based setup is reconfigurable, tracking up to four events in parallel without missing a beat. From Hanbury-Brown-Twiss experiments to decoding pulse-position modulated (PPM) data, it’s an all-in-one toolkit for photon wranglers. [Jason] will go deeper into the subject and do a few live experiments.

Measuring single photons can be achieved with photomultipliers as well. If exploring the possibilities of FPGA’s is more your thing, consider reading this article.

Cheap FPGA PCIe Development

December 7, 2024 by 18 Comments

Typically, if you want to build an FPGA project inside a PC, you’d need a fairly expensive development board that plugs into the bus. However, [CircuitValley] found some IBM RS-485 boards that are little more than a PCIe board with an Intel FPGA onboard. These are widely avaiable on the surplus market for around $20 shipped. He’s been documenting how to use them.

The FPGA onboard is a Cyclone IV with about 21,000 logic elements and a little over 750 kbits of memory. The board itself has configuration memory, power management, and a few connectors. The JTAG header is unpopulated, but the footprint is there. You simply need to supply a surface-mount pin header and an external JTAG probe, and you can program. Even if you aren’t interested in using an FPGA board, the reverse engineer steps are fun to watch.

The situation reminds us a little of the RTL-SDR — when a device uses a programmable device to perform nearly all of its functions, it is subject to your reprogramming. What would you do with a custom PCIe card? You tell us. Need a refresher on the bus? We can help. Thinking of building some sort of FPGA accelerator? Maybe try RIFFA.

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A Really Low Level Guide To Doing Ethernet On An FPGA

August 14, 2024 by 7 Comments

With so much of our day-to-day networking done wirelessly these days, it can be easy to forget about Ethernet. But it’s a useful standard and can be a great way to add a reliable high-throughput network link to your projects. To that end, [Robert Feranec] and [Stacy Rieck] whipped up a tutorial on how to work with Ethernet on FPGAs. 

As [Robert] explains, “many people would like to transfer data from FPGA boards to somewhere else.” That basically sums up why you might be interested in doing this. The duo spend over an hour stepping through doing Ethernet at a very low level, without using pre-existing IP blocks to make it easier. The video explains the basic architecture right down to the physical pins on the device and what they do, all the way up to the logic blocks inside the device that do all the protocol work.

If you just want to get data off an embedded project, you can always pull in some existing libraries to do the job. But if you want to really understand Ethernet, this is a great place to start. There’s no better way to learn than doing it yourself. Files are on GitHub for the curious. Continue reading “A Really Low Level Guide To Doing Ethernet On An FPGA” →

Comparing X86 And 68000 In An FPGA

June 7, 2024 by 15 Comments

[Michael Kohn] started programming on the Motorola 68000 architecture and then, for work reasons, moved over to the Intel x86 and was not exactly pleased by the latter chip’s perceived shortcomings. In the ’80s, the 68000 was a very popular chip, powering everything from personal computers to arcade machines, and looking at its architecture and ease of programming, you can see why this was.

Fast-forward a few years, and [Michael] decided to implement both cores in an FPGA to compare real applications, you know, for science. As an extra bonus, he also compares the performance of a minimal RISC-V implementation on the same hardware, taken from an earlier RISC-V project (which you should also check out !)

Utilizing their ‘Java Grinder’ application (also pretty awesome, especially the retro console support), a simple Mandelbrot fractal generator was used as a non-trivial workload to produce binaries for each architecture, and the result was timed. Unsurprisingly, for CISC architectures, the 68000 and x86 code sizes were practically identical and significantly smaller than the equivalent RISC-V. Still, looking at the execution times, the 68000 beat the x86 hands down, with the newer RISC-V speeding along to take pole position. [Michael] admits that these implementations are minimal, with no pipelining, so they could be sped up a little.

Also, it’s not a totally fair race. As you’ll note from the RISC-V implementation, there was a custom RISC-V instruction implemented to perform the Mandelbrot generator’s iterator. This computes the complex operation Z = Z2 + C, which, as fellow fractal nerds will know, is where a Mandelbrot generator spends nearly all the compute time. We suspect that’s the real reason RISC-V came out on top.

If actual hardware is more your cup of tea, you could build a minimal 68k system pretty easily, provided you can find the chips. The current ubiquitous x86 architecture, as odd as it started out, is here to stay for the foreseeable future, so you’d just better get comfortable with it!

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