VexRiscv: A Modular RISC-V Implementation for FPGA

Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.

SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.

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Simulating the Learn-by-Fixing CPU

Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool called EDA Playground. This time, I’ll take you through the code details and how to run the simulation.

You’ll want to refer to the previous post if you didn’t read it already. The diagrams and tables give a high-level overview that will help you understand the files discussed in this post.

If you wanted to actually program this on a real FPGA, you’d have a little work to do. The memory and register initialization is done in a way that works fine for simulation, but wouldn’t work on a real FPGA. Anyway, let’s get started!

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Learn by Fixing: Another Verilog CPU

Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.

The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. However, what was worse is one of the modules needed to get it to work was missing! You might argue it was an exercise left to the reader, but it probably should have been pointed out that way.

At first, I was ready to delete the bookmark and move on. Then I decided that the process of fixing this design and doing a little analysis on it might actually be more instructive than just studying a fully working design. So I decided to share my fix with you and look inside the architecture a bit more. On top of that, I’ll show you how to get the thing to run in an online simulator so you can experiment with no software installation. Of course, if you are comfortable with a Verilog toolchain (like the ones from Xilinx or Altera, or even free ones like Icarus or CVer) you should have no problem making that work, either. This time I’ll focus on how the CPU works and next time I’ll show you how to simulate it with some free tools. Continue reading “Learn by Fixing: Another Verilog CPU”

FPGAs in C with Cynth

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a hardware description language. One of these, cynth, is simple to use and available on GitHub. You will need to install scala and a build system called sbt, if you want to try it.

There are limitations, of course. If you want a preprocessor, you’ll have to run it separately. You can’t use global variables, multiplication, floats, and many other pieces of C. The compiler generates a Verilog file for each C function.
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Zork Comes to Custom FPGA CPU (Again)

[Robert Baruch] wanted to tackle a CPU project using an FPGA. One problem you always have is you can either mimic something that has tools and applications or  you can go your own way and just build everything from scratch (which is much harder).

[Robert] took the mimic approach–sort of. He built a CPU with the express idea of running Infocom’s Z-machine virtual machine, which allows it to play Zork. So at least when you are done, you don’t have to explain to your non-tech friends that it only blinks an LED. Check out the video, below, for more details.

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Mag Lev Without The Train (But With An FPGA)

It always surprises us that magnetic levitation seems to have two main purposes: trains and toys. It is reasonably inexpensive to get floating Bluetooth speakers, globes, or just floating platforms for display. The idea is reasonably simple, especially if you only care about levitation in two dimensions. You let an electromagnet pull the levitating object (which is, of course, ferrous). A sensor detects when the object is at a certain height and shuts off the magnet. The object falls, which turns the magnet back on, repeating the process. If you do it right, the object will reach equilibrium and hover near the sensor.

Some students at Cornell University decided to implement the control loop to produce levitation using an Altera FPGA. An inductive sensor determined the position of an iron ball. The device uses a standard proportional integral derivative (PID) control loop. The control loop and PWM generation occur in the FPGA hardware. You can see a video of their result, below.

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Crawl, Walk, Run: A Starter CPU

Last time I talked about getting started with CPU design by looking at older designs before trying to tackle a more modern architecture. In particular, I recommended Caxton Foster’s Blue, even though (or maybe because) it was in schematic form. Even though the schematics are easy to understand, Blue does use a few dated constructs and you probably ought to build your take on the design using your choice of VHDL or Verilog.

In my case, my choice was Verilog. You can find my implementation of Blue on Opencores.org. I made quite a few changes to Foster’s original design. For example, armed with semiconductor memory, I managed to get all instructions to operate in one major cycle (which is, of course, 8 minor cycles). I also modernized the clock generation and added some resources and instructions.

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