Physical Neural Network Can Be Trained Like A Digital One

July 20, 2023 by Donald Papp 11 Comments

Here’s an unusual concept: a computer-guided mechanical neural network (video, embedded below.) Why would one want a mechanical neural network? It’s essentially a tool to explore what it would take to make physical materials work in nonstandard ways. The main part is a lattice of interlinked mechanical components. When one applies a certain force in a certain direction on one end, it causes the lattice to deform in a non-intuitive way on the other end.

To make this happen, individual mechanical elements in the lattice need to have their compliance carefully tuned under the guidance of a computer system. The mechanisms shown can be adjusted on demand while force is applied and cameras monitor the results.

This feedback loop allows researchers to use the same techniques for training neural networks that are used in machine learning applications. Ultimately, a lattice can be configured in such a way that when side A is pressed like this, side B moves like that.

We’ve seen compliant structures that move in unexpected ways before, and they are always fascinating. One example is this 3D-printed door latch that translates a twisting motion into a linear one. Research into physical neural networks seems like it might open the door to more complex systems, or provide insights into metamaterial design.

You can watch the video below just under the page break, or if you prefer, skip the intro and jump straight into How It Works at [2:32].

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ICEBlaster: A Drag’n’Drop Bitstream Loader For ICE40

July 11, 2022 by Dave Rowntree 10 Comments

The iCE40 series of FPGAs gets a fair bit of coverage on these pages, largely due to its accessibility (thanks to huge efforts in reverse engineering and open tool chains) and likely also due to Lattice Semiconductors’ attitude to open source in general. Whilst these devices are small and rather limited, you can’t really beat them for a first foray into the subject. They’re plenty beefy enough for many of the simpler FPGA applications. [TinLethax] over on Hackaday.IO has plenty of experience with the devices, and has added another tool to our collective iCE40 arsenal, namely iCEBlaster, a USB mass storage device (MSC) style bootloader for drag-n-drop bitstream loading. The days of needing dedicated special programmers are starting to be numbered, with many chips now presenting a USB mass storage device to the host in order to upload the firmware image.

FPGAs don’t tend to operate this way, needing a device-specific bitstream loading upon start-up, which (unless they have OTP memory) is usually the job of an external configuration memory. iCEBlaster (a play on the Xilinx ByteBlaster programmer, maybe?) runs on the STM32F4xx series devices at least, but should be easily portable to others. The idea is pretty straightforward — dragging a new bitstream file onto the storage device initiates an FPGA target reset, which in turn allows the STM32 to send the bitstream over to the iCE40 via the SPI interface. Nothing more than that.

If you’ve been looking to get into the iCE40, this guide might be a good starting point, and every learning experience needs a good project to drive it, how about running Doom on a softcore RISC-V?

FPGA Starter Videos To Help Soften That Learning Curve

February 17, 2022 by Dave Rowntree 8 Comments

Digi-Key have been producing YouTube videos for a number of years now, and if you weren’t aware, they’re definitely worthy of some viewing time. The playlist we’re highlighting here is a pretty good introduction to FPGAs, specifically those supported by open source tools, with low cost hardware. If you’ve always wanted to get into hacking FPGA platforms, but don’t know where to start, this is going to be a big help. After first covering what an FPGA is and is not, and why you want to use one, [Shawn Hymel] dives in to the toolchain.

We’re really lucky that the bitstream for the Lattice iCE40 was reverse engineered by the super talented Claire (née Clifford) Wolf (AMP hour interview) which enabled the project ICEstorm toolchain to be created. Leveraging Yosys for synthesis and logic mapping, Icarus verilog coupled with GTKwave for simulation, netpnr for place and route and finally the project ICEstorm bitstream tools for packing into iCE40 format and loading onto the hardware. The whole toolchain flow is managed by APIO for simplicity, that is, provided your FPGA board is supported!

Of course, [Shawn] is using the low cost (for an FPGA) ICEStick by Lattice for this tutorial series, and they’re currently hard to get (you know why by now!) but, there are many other boards you could use. If you want to play with applications coupling a ARM micro to an FPGA, then the excellent BlackIce Mx is an option, but there are many other boards now with an decent micro nestled next to an FPGA and a few peripherals for convenience.

We should mention here, that project ICEstorm and the iCE40 is not the only show in town. Project Trellis has had our eye for a while, which targets the more complex Lattice ECP5 device. Yosys and friends do support more architectures, but the available flows usually require at least some vendor tool support at this time (looking straight at you, Xilinx) but as more devices get decoded, the open source tools will grow, and we will bring you that news!

What’s nice about this Digi-Key YT series, is that it doesn’t just cover the basic toolchain flow, then drop you in at the deep end of a big learning curve. There are videos covering subjects such as finite state machines (FSMs), test-benching and simulation, using embedded (block) memories, PLLs, harder subjects like dealing with metastability and clock-domain crossing (OK, he covers one technique – there’s more than one way to skin that particular cat) before finally looking at soft cores like the RISC-V. Lots to learn, and pretty well executed if you ask us! A Github version is available, for those who can’t stand watching the videos!

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Printing, Plating, And Baking Makes DIY Microlattices Possible

August 19, 2020 by Dan Maloney 15 Comments

To be honest, we originally considered throwing [Zachary Tong]’s experiments with ultralight metallic microlattices into the “Fail of the Week” bucket. But after watching the video below for a second time, it’s just not fair to call this a fail, so maybe we’ll come up with a new category — “Qualified Success of the Week”, perhaps?

[Zachary]’s foray into the strange world of microlattices began when he happened upon a 2011 paper on the subject in Science. By using a special photocurable resin, the researchers were able to use light shining through a mask with fine holes to create a plastic lattice, which was then plated with nickel using the electroless process, similar to the first half of the electroless nickel immersion gold (ENIG) process used for PCBs. After removing the resin with a concentrated base solution, the resulting microlattice is strong, stiff, and incredibly light.

Lacking access to the advanced materials and methods originally used, [Zachary] did the best he could with what he had. An SLA printer with off-the-shelf resin was used to print the skeleton using the same algorithms used in the original paper. Those actually turned out pretty decent, but rather than electroless plating, he had to go with standard electroplating after a coat of graphite paint. The plated skeletons looked great — until he tried to dissolve the resin. When chemical approaches failed, into the oven went the plated prints. Sadly, it turns out that the polymers in the resin expand when heated, which blew the plating apart. A skeleton in PLA printed on an FDM printer fared little better; when heated to drive out the plastic, it became clear that the tortuous interior of the lattice didn’t plate very well.

From aerogels to graphene, we love these DIY explorations of new and exotic materials, so hats off to [Zachary] for giving it a try in the first place.

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Lattice Drops EULA Clause Forbidding FPGA Bitstream Reverse Engineering

June 6, 2020 by Jenny List 33 Comments

Yesterday we reported that Lattice Semiconductor had inserted a clause that restricted the reverse engineering of bitstreams produced by their FPGA toolchains. Although not explicitly stated, it’s assumed that this was directed toward several projects over the past five years that have created fully open source toolchains by reverse engineering the bitstream protocols of the Lattice ICE40 and ECP5 FPGA architectures. Late yesterday Lattice made an announcement reversing course.

To the open source community, thank-you for pointing out a new bitstream usage restriction in the Lattice Propel license. We are excited about the community’s engagement with Lattice devices and our intent is to not hinder the creation of innovative open source FPGA tools.

It’s refreshing then to see this announcement from Lattice Semiconductor. Even more so is the unexpected turn of speed with which they have done so, within a couple of days of it being discovered by the open-source community. We report depressingly often on boneheaded legal moves from corporations intent on curbing open source uses of their products. This announcement from Lattice removes what was an admonition opposing open source toolchains, can we hope that the company will continue yesterday’s gesture and build a more lasting relationship with the open source community?

The underlying point to this story is that in the world of electronics there has long been an understanding that hardware hackers drive product innovation which will later lead to more sales. Texas Instruments would for years supply samples of exotic semiconductors to impecunious students for one example, and maybe you have a base-model Rigol oscilloscope with a tacitly-approved software hack that gives it an extra 50MHz of bandwidth for another.

We can only congratulate Lattice on their recognition that open source use of their products is beneficial for them, and wish that some of the other companies triggering similar stories would see the world in the same way. Try interacting more with your open source fans; they know and love your hardware more than the average user and embracing that could mean a windfall for you down the road.

Lattice Semiconductor Targets Bitstream Reverse Engineering In Latest Propel SDK License

June 5, 2020 by Maya Posch 42 Comments

The topic of reverse engineering is highly contentious at best when it comes to software and hardware development. Ever since the configuration protocol (bitstream) for Lattice Semiconductor’s iCE40 FPGAs was published in 2015 through reverse engineering efforts, there has been a silent war between proponents of open bitstream protocols and FPGA manufacturers, with the Lattice ECP5’s bitstream format having been largely reverse-engineered at this point.

Update: About eight hours after this article was published, Lattice Semiconductor issued a statement retracting the EULA language that banned bitstream reverse engineering. Please check out Hackaday’s article about this reversal.

Most recently, it appears that Lattice has fired a fresh shot across the bow of the open source projects. A recently discovered addition to the Propel SDK, which contains tools to program and debug Lattice devices, specifically references bitstream reverse engineering. When logged in with an account on the company’s website the user must agree to the Lattice Propel License Agreement for Lattice Propel 1.0 prior to download. That document includes the following language:

In particular, no right is granted hereunder […] (3) for reverse engineering a bitstream format or other signaling protocol of any Lattice Semiconductor Corporation programmable logic device.

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Mithro Runs Down Open Source FPGA Toolchains

March 6, 2020 by Elliot Williams 28 Comments

Tim [Mithro] Ansell has a lot to tell you about the current state of open FPGA tooling: 115 slides in 25 minutes if you’re counting. His SymbiFlow project aims to be the GCC of FPGA toolchains: cross-platform, multi-platform, completely free, and all-encompassing. That means that it’s an umbrella framework for all of the work that everyone else is doing, from work on synthesis and verification tools, to placing and routing, to vendor-specific chip libraries. His talk catches you up with the state of the art at the end of 2019, and it’s embedded below. Spoiler alert: SymbiFlow has the big Xilinx 7-series FPGAs in its crosshairs, and is closing in. SymbiFlow is that close to getting a networked Linux system on the FPGA fabric in a Xilinx 7 today, completely independent of any vendor tools.

But let’s step back a sec for a little background. When you code for an FPGA, words you type get turned into a bitstream of ones and zeroes that flip perhaps a few million switches inside the chip. Going from a higher-level language to a bitstream is a lot like compiling normal programming languages, except with the twist that the resulting computational logic doesn’t map straight into a machine language, but rather into lower-level physical hardware on the FPGA. So “compilation” for FPGAs involves two steps: synthesis and place-and-routing. Synthesis takes the higher-level language that you write and turns it into a set of networks and timing requirements that represent the same logic, and can work across chip families. Yosys is the open-source synthesis tool of choice here.