STM32 Analog Converter Phase Noise

[Avian] has been using STM32 ARM processors to sample RF for a variety of applications. At first, he was receiving relatively wide TV signals. Recently, though, he’s started dealing with very narrow signals and he found that his samples had a lot of spread in the frequency domain that he didn’t expect.

What followed was some detective work that resulted in a determination that phase noise was the culprit. But why? [Avian] took some measurements and noticed that the phase noise almost exactly matched the phase noise specification for the STM32’s phase locked loop (PLL).

Unfortunately, there didn’t seem to be a good way to avoid using the PLL without major changes to the rest of the circuit. However, it was quite the learning experience and something to be aware of when counting on built-in converters for high-accuracy measurements.

One of the best things about this post is the references to more information. There’s a great explanation of phase noise, as well as a specific application note about clock jitter and analog converters.

We’ve talked about phase noise in direct digital synthesis a few times. But usually, it is pretty obvious like when you are asking a CPU to double as an RF transmitter. [Avian’s] post was a bit more of a detective story.

Unlock the Phase Locked Loop

If you want a stable oscillator, you usually think of using a crystal. The piezoelectric qualities of quartz means that it can be cut in a particular way that it will oscillate at a very precise frequency. If you present a constant load and keep the temperature stable, a crystal oscillator will maintain its frequency better than most other options.

There are downsides to crystals, though. As you might expect, because crystals are so stable it’s hard to change the frequency much when you want a different one. You can use a trimming capacitor to pull the frequency a little, but to really change frequency, you have to change crystals.

There are other kinds of oscillators that are more frequency agile. However, they aren’t usually as stable. To combine flexibility with crystal-like stability, you can use a Phase Locked Loop (PLL). Many modern systems use direct digital synthesis, but the PLL is a venerable and time-tested technique.

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Generate Clocks with the SI5351 and an Arduino

If you’re dealing with RF, you’ll probably have the need to generate a variety of clock signals. Fortunately, [Jason] has applied his knowledge to build a SI5351 library for the Arduino and a breakout board for the chip.

The SI5351 is a programmable clock generator. It can output up to eight unique frequencies at 8 kHz to 133 MHz. This makes it a handy tool for building up RF projects. [Jason]’s breakout board provides 3 isolated clock outputs on SMA connectors. A header connects to an Arduino, which provides power and control over I2C.

If you’re looking for an application, [Jason]’s prototype single-sideband radio shows the chip in action. This radio uses two of the SI5351 clocks: one for the VFO and one for the BFO. This reduces the part count, and could make this design quite cheap.

The Arduino library is available on Github, and you can order a SI5351 breakout board from OSHPark.

Intro to Phase-Locked Loops

[Kenneth Finnegan] put up a lengthy primer on PLLs (Phase-Locked Loops). We really enjoyed his presentation (even the part where he panders to Rigol for a free scope… sign us up for one of those too). The concepts behind a PLL are not hard to understand, and [Kenneth] managed to come up with a handful of different demonstrations that really help to drive each point home.

A PLL is made up of three parts: a phase detector, a low pass filter, and a voltage controlled oscillator. It can do really neat things, like multiply clock speed (you see them in beefier chips like the ARM architecture all the time). The experiments seen in the video use a CD4046 chip which has two different types of phase detectors. The two signals displayed on the oscilloscope above compare the incoming clock signal with the output from the VCO. Depending on the type of phase detector used, and the quality of the low-pass filter, these might be tightly synchronized or wildly unstable. Find out why by watching the video embedded after the break.

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PLL 101

[Jeri Ellsworth] and former Commodore Computer engineer and current full time tinkerer [Bil Herd] have a little chat on skype covering the 101’s of Phase Lock Loops in this hour long video. PLL’s are handy for many applications, but their basic use is to keep clock signals in sync.

Topics covered include: Why we care, a basic explanation for the CD4046, capture ranges, and meta stability. Examples from analog tv, to clock recovery, finding falling edges and FPGA’s. This thing is jam packed full of information.

With talks of future episodes and a quick tour of [Bil’s] bench this is something to not miss. Join us after the break for the video!

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