Intro to Phase-Locked Loops

[Kenneth Finnegan] put up a lengthy primer on PLLs (Phase-Locked Loops). We really enjoyed his presentation (even the part where he panders to Rigol for a free scope… sign us up for one of those too). The concepts behind a PLL are not hard to understand, and [Kenneth] managed to come up with a handful of different demonstrations that really help to drive each point home.

A PLL is made up of three parts: a phase detector, a low pass filter, and a voltage controlled oscillator. It can do really neat things, like multiply clock speed (you see them in beefier chips like the ARM architecture all the time). The experiments seen in the video use a CD4046 chip which has two different types of phase detectors. The two signals displayed on the oscilloscope above compare the incoming clock signal with the output from the VCO. Depending on the type of phase detector used, and the quality of the low-pass filter, these might be tightly synchronized or wildly unstable. Find out why by watching the video embedded after the break.

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PLL 101

[Jeri Ellsworth] and former Commodore Computer engineer and current full time tinkerer [Bil Herd] have a little chat on skype covering the 101′s of Phase Lock Loops in this hour long video. PLL’s are handy for many applications, but their basic use is to keep clock signals in sync.

Topics covered include: Why we care, a basic explanation for the CD4046, capture ranges, and meta stability. Examples from analog tv, to clock recovery, finding falling edges and FPGA’s. This thing is jam packed full of information.

With talks of future episodes and a quick tour of [Bil's] bench this is something to not miss. Join us after the break for the video!

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