A Radio Transceiver From A Cable Modem Chipset

August 31, 2019 by Jenny List 11 Comments

It’s a staple of our community’s work, to make electronic devices do things their manufacturers never intended for them. Analogue synthesisers using CMOS logic chips for example, or microcontrollers that bitbang Ethernet packets without MAC hardware. One of the most fascinating corners of this field comes in the form of software defined radios (SDRs), with few of us not owning an RTL2832-based digital TV receiver repurposed as an SDR receiver.

The RTL SDR is not the only such example though, for there is an entire class of cable modem chipsets that contain the essential SDR building blocks. The Hermes-Lite is an HF amateur radio transceiver project that uses an AD9866 cable modem chip as the signal end for its 12-bit SDR transceiver hardware with an FPGA between it and an Ethernet interface. It covers frequencies from 0 to 38.4 MHz, has 384 kHz of bandwidth, and can muster up 5W of output power.

It’s a project that’s been on our radar for the past few years, though somewhat surprisingly this is the first mention of it here on Hackaday. Creator [Steve Haynal] has reminded us that version 2 is now a mature project on its 9th iteration, and says that over 100 “Hermes-Lite 2.0” units have been assembled to date. If you’d like a Hermes-Lite of your own it’s entirely open-source, and they organise group buys of the required components.

Of course, SDRs made from unexpected components don’t have to be exotic.

Your Arduino SAMD21 ADC Is Lying To You

August 30, 2019 by Ted Yapo 64 Comments

One of the great things about the Arduino environment is that it covers a wide variety of hardware with a common interface. Importantly, this isn’t just about language, but also about abstracting away the gory details of the underlying silicon. The problem is, of course, that someone has to decode often cryptic datasheets to write that interface layer in the first place. In a recent blog post on omzlo.com, [Alain] explains how they found a bug in the Arduino SAMD21 analogRead() code which causes the output to be offset by between 25 mV and 57 mV. For a 12-bit ADC operating with a reference of 3.3 V, this represents a whopping error of up to 70 least-significant-bits!

Excerpt from the SAMD wiring_analog.c file in the Arduino Core repo.

While developing a shield that interfaces to 24 V systems, the development team noticed that the ADC readings on a SAMD21-based board were off by a consistent 35 mV; expanding their tests to a number of different analog pins and SAMD21 boards, they saw offsets between 25 mV and 57 mV. It seems like this offset was a known issue; Arduino actually provides code to calibrate the ADC on SAMD boards, which will “fix” the problem with software gain and offset factors, although this can reduce the range of the ADC slightly. Still, having to correct for this level of error on a microcontroller ADC in 2019 — or even 2015 when the code was written — seems really wrong.

After writing their own ADC read routine that produced errors of only between 1 mV and 5 mV (1 to 6 LSB), the team turned their attention to the Arduino code. That code disables the ADC between measurements, and when it is re-enabled for each measurement, the first result needs to be discarded. It turns out that the Arduino code doesn’t wait for the first, garbage, result to finish before starting the next one. That is enough to cause the observed offset issue.

It seems odd to us that such a bug would go unnoticed for so long, but we’ve all seen stranger things happen. There are instructions on the blog page on how to quickly test this bug. We didn’t have a SAMD21-based Arduino available for testing before press time, but if you’ve got one handy and can replicate these experiments to verify the results, definitely let us know in the comments section below.

If you don’t have an Arduino board with a SAMD21 uC, you can find out more about them here.

Arduino On MBed

August 30, 2019 by Al Williams 22 Comments

Sometimes it seems like Arduino is everywhere. However, with a new glut of IoT processors, it must be quite a task to keep the Arduino core on all of them. Writing on the Arduino blog, [Martino Facchin], Arduino’s chief of firmware development, talks about the problem they faced supporting two new boards from Nordic.

The boards, the Nano 33 BLE and Nano 33 BLE Sense are based on an ARM Cortex M4 CPU from Nordic. The obvious answer, of course, is to port the Arduino core over from scratch. However, the team didn’t want to spend the time for just a couple of boards. They considered using the Nordic libraries to interact with the hardware, but since that is closed source, it didn’t really fit with Arduino’s sensitivities. However, in the end, they took a third approach which could be a very interesting development: they ported the Arduino core to the Mbed OS. There’s even an example of loading a sketch on top of Mbed available from [Jan Jongboom].

Continue reading “Arduino On MBed” →

New Cray Will Reach 1.5 ExaFLOPS

August 27, 2019 by Al Williams 61 Comments

It wasn’t that long ago when hard drives that boasted a terabyte of capacity were novel. But impressive though the tera- prefix is, beyond that is peta and even further is exa — as in petabyte and exabyte. A common i7 CPU currently clocks in at about 60 gigaflops (floating point operations per second). Respectable, but today’s supercomputers routinely turn in sustained rates in the petaflop range, with some even faster. The Department of Energy announced they were turning to Cray to provide three exascale computers — that is, computers that can reach an exaflop or more. The latest of these, El Capitan, is slated to reach 1.5 exaFLOPS and will reside at Lawrence Livermore National Laboratories.

The $600 million price tag for El Capitan seems pretty reasonable for a supercomputer. After all, a Cray I could only do 160 megaflops and cost nearly $8 million in 1977, or about $33 million in today’s money. So about 20 times the cost gets them over 9,000 times the compute power.

Continue reading “New Cray Will Reach 1.5 ExaFLOPS” →

GigaDevice Releasing RISC-V MCUs And Development Boards

August 27, 2019 by Maya Posch 30 Comments

Probably not too many people have heard of Chinese manufacturer GigaDevice who so far has mostly been known as a NOR Flash memory manufacturer. Their GD32 range of MCUs is however STM32-compatible, making them interesting (cheaper) alternatives to sourcing directly from ST. Now GigaDevice has announced during a presentation that they are releasing a range of RISC-V-based MCUs: the GD32V series.

As GigaDevice has not yet updated their English-language website, the information we do have is based on CNX-Software‘s translations from Chinese. The specs for the GD32VF103 series of MCUs are listed by them as follows:

Core – GD32VF103 RISC-V “Bumblebee Core” @ 108 MHz
Memory – 8KB to 32KB SRAM
Storage – 16KB to 128KB flash
Peripherals – USB OTG and CAN 2.0B
I/O – 3.3V, 5V tolerant
Supply Voltage – 2.6 to 3.6V
Package – QFN36, LQFP48, LQFP64, and LQFP100 packages

Whether they are pin-compatible with the GD32 MCUs is still to be confirmed. If that turns out to be the case, then this might be an interesting drop-in solution for some products. From the specs it seems clear that they are targeting the lower-end ARM-based MCUs such as ST’s Cortex-M3-based STM32F103, which are quite common in a large range of embedded systems.

Seeing a performance comparison between both types of MCU would be interesting to see as lower power usage and higher efficiency compared to the ARM cores is being claimed. Both MCUs and development boards are already available for sale at Tmall, with the basic GD32VF103C-START board going for about $11 and the GD32VF103TBU6 MCU (QFN36, 64 kB Flash) for roughly $1.27.

Documentation and SDKs in English seem to be a bit scarce at this point, but hopefully before long we too will be able to use these MCUs without having to take up Chinese language classes.

Thanks to [Flaviu] for the tip!

The Satellite Phone You Already Own: From Orbit, UbiquitiLink Will Look Like A Cell Tower

August 26, 2019 by Dan Maloney 54 Comments

For anyone that’s ever been broken down along a remote stretch of highway and desperately searched for a cell signal, knowing that a constellation of communications satellites is zipping by overhead is cold comfort indeed. One needs specialized gear to tap into the satphone network, few of us can justify the expense of satellite phone service, and fewer still care to carry around a brick with a chunky antenna on it as our main phone.

But what if a regular phone could somehow leverage those satellites to make a call or send a text from a dead zone? As it turns out, it just might be possible to do exactly that, and a Virginia-based startup called UbiquitiLink is in the process of filling in all the gaps in cell phone coverage by orbiting a constellation of satellites that will act as cell towers of last resort. And the best part is that it’ll work with a regular cell phone — no brick needed.

Continue reading “The Satellite Phone You Already Own: From Orbit, UbiquitiLink Will Look Like A Cell Tower” →

ORNL's Summit supercomputer, fastest until 2020 (Credit: ORNL)

Joining The RISC-V Ranks: IBM’s Power ISA To Become Free

August 23, 2019 by Maya Posch 38 Comments

IBM’s Power processor architecture is probably best known today as those humongous chips that power everything from massive mainframes and supercomputers to slightly less massive mainframes and servers. Originally developed in the 1980s, Power CPUs have been a reliable presence in the market for decades, forming the backbone of systems like IBM’s RS/6000 and AS/400 and later line of Power series.

Now IBM is making the Power ISA free to use after first opening up access to the ISA with the OpenPower Foundation. Amidst the fully free and open RISC-V ISA making headway into the computing market, and ARM feeling pressured to loosen up its licensing, it seems they figured that it’s best to join the party early. Without much of a threat to its existing business customers who are unlikely to whip up their own Power CPUs in a back office and not get IBM’s support that’s part of the business deal, it seems mostly aimed at increasing Power’s and with it IBM’s foothold in the overall market.

The Power ISA started out as the POWER ISA, before it evolved into the PowerPC ISA, co-developed with Motorola and Apple and made famous by Apple’s use of the G3 through G5 series of PowerPC CPUs. The PowerPC ISA eventually got turned into today’s Power ISA. As a result it shares many commonalities with both POWER and PowerPC, being its de facto successor.

In addition, IBM is also opening its OpenCAPI accelerator and OpenCAPI Memory Interface variant that will be part of the upcoming Power9′ CPU. These technologies are aimed at reducing the number of interconnections required to link CPUs together, ranging from NVLink, to Infinity Fabric and countless more, not to mention memory, where OMI memory could offer interesting possibilities.

Would you use Power in your projects? Let us know in the comments.